參數(shù)資料
型號(hào)： DLKPC192S
英文描述： 10Gbps Ethernet LAN Physical Coding Sublayer (PCS) Device
中文描述： 10Gbps的以太網(wǎng)物理編碼子層（PCS）設(shè)備
文件頁(yè)數(shù)： 15/25頁(yè)
文件大?。?/td> 360K
代理商： DLKPC192S
!
SLLS536
–
AUGUST 2002
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Table 10. Transmitter and Receiver Control Bit Definitions (Register 18)
BIT(S)
NAME
DESCRIPTION
READ/WRITE
18.15:10
MDIO_DEL_SPC[5:0]
Minimum number of deletable idle words that must be passed between deletion events.
Default is 16.
Read/write
18.9
MDIO_RCNT_EBL
Transmission start up delay enable. Controls whether a minimum of eight idle words
must be detected on the XGMII transmit path before the transmit path is enabled.
Default is 1, enabled.
Read/write
18.8
MDIO_AKR_NI
Reads value from I/O terminal.
Read-only
18.7:0
NOTE: Power-on reset value (IDLE MODE): 0x4200.
Power-on reset value (AKR MODE): 0x4300.
Reserved
Read returns 0.
Read-only
Table 11. Test Mode Bit Definitions (Register 19)
BIT(s)
NAME
DESCRIPTION
READ/WRITE
19.15:11
Reserved
Read returns 0.
Read-only
19.10
MDIO_RXC_BYPASS
Bypass receive decomposer
Read/write
19.9
MDIO_RXS_BYPASS
Bypass receive descrambler
Read/write
19.8
MDIO_TXC_BYPASS
Bypass transmit composer
Read/write
19.7
MDIO_TXS_BYPASS
Bypass transmit scrambler
Read/write
19.6:0
NOTE: Power-on reset value: 0x0000.
These bits are intended for test only and should not be programmed to any value except 0x0000.
Reserved
These bits must be maintained at the default value of 0.
Read/write
IPG modes
The XGMII interface transports information that consists of packets and interpacket gap (IPG) characters. While
the proposed IEEE 802.3ae standard defines that the IPG, when transferred over the XGMII interface, consists
of idle characters, industry practice has also defined a mode in which the IPG consists of other characters. This
alternative mode character set is that used by XAUI devices to replace the idles within the IPG. This character
set consists of alignment characters (A), control characters (K) and replacement characters (R).
The DLKPC192S can operate in one of two modes: AKR mode or idle mode. The configuration control terminal
AKR_NI selects the mode.
In AKR mode, AKR_NI = 1, the DLKPC192S converts all AKR characters to idle characters, performs insertion
or deletion on the idle characters, and transmits only encoded idle characters out the XSBI interface. The
receive channel expects encoded idle characters to enter the XSBI, and performs insertions and deletions on
idle characters only.
In idle mode, AKR_NI = 0, the DLKPC192S expects the IPG to consist of a sequence of idle characters on the
XGMII interface and encoded idle characters on the XBSI interface. Both the transmit and receive FIFOs rely
upon a valid idle stream to perform clock tolerance compensation.
In sumamry, if the system in which the DLKPC192S is placed presents AKR characters on the XGMII transmit
input interface, the AKR_NI pin must be set high. If the system presents idle characters on the XGMII input, the
AKR_NI pin must be set low. In both configurations, the device always outputs idle characters on the XGMII
receive output interface and encoded idle characters on the XSBI transmit output interface. In addition, the
device always requires encoded idle characters to be available on the XSBI receive input interface. Finally, the
DLKPC192S is not able to perform clock tolerance compensation on local fault characters (LF) or remote fault
characters (RF), so the IPG must contain some idle characters during these conditions.
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