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參數(shù)資料
| 型號： | DLKPC192S |
| 英文描述： | 10Gbps Ethernet LAN Physical Coding Sublayer (PCS) Device |
| 中文描述： | 10Gbps的以太網(wǎng)物理編碼子層（PCS）設(shè)備 |
| 文件頁數(shù)： | 23/25頁 |
| 文件大小： | 360K |
| 代理商： | DLKPC192S |
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SLLS536
–
AUGUST 2002
23
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
XGMII (continued)
50%
50%
RC
RD(31:0)
KF(3:0)
t(SETUP)
t(SETUP)
t(PERIOD)
Valid Data
Valid Data
Valid Data
Figure 15. XGMII Receive Timing Diagram
Table 15. XGMII Receive AC Specification
PARAMETER
MIN
TYP
MAX
UNIT
t(PERIOD)
t(SETUP)
t(HOLD)
t(DUTY)
RD5, RD9, RD10, and RD11 do not meet the IEEE specification of 960 ps, RD5 being the worst channel with the least setup time. There exists
excess hold margin, the minimum hold time being 1.3 ns, to allow for board-level clock delay to meet the IEEE 960-ns setup-time requirement.
RC receive clock (received by DLKPC192S)
6.4
ns
Data-setup to rising or falling edge of RC
650
ps
Data-hold from rising or falling edge of RC
960
ps
RC duty cycle
40%
60%
MDIO
The technology and timing for the MDIO interface was under flux within the 802.3ae task force during the
definition of the DLKPC192S. In the DLKPC192S, the MDIO interface technology was chosen to be LVTTL.
testability
Test functionality was added to the DLKPC192S to support device evaluation and test during manufacturing.
This functionality is intended for use by Texas Instruments. The TEST input signal, if set to 1, enables various
test modes. When TEST is true, some of the input and output signals of the DLKPC192S may change
functionality.
While harm to the device is not likely to occur if TEST modes are enabled, users of the DLKPC192S are advised
to tie the TEST terminal to 0 at all times.
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