!
SLLS536
–
AUGUST 2002
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Table 7. Vendor Unique Registers
REGISTER ADDRESS
REGISTER NAME
16
Transmitter status
17
Receive status
18
TX and RX control
19
Test mode control
20
–
31
Reserved
Table 8. Transmitter Status Bit Definitions (Register 16)
BIT(S)
NAME
DESCRIPTION
READ/WRITE
16.15
TXI_OVFL
Transmit FIFO has detected an overflow error. Event is latched to ensure observability.
Read-only
Self-clearing
16.14
TXI_UNFL
Transmit FIFO has detected an underflow error. Event is latched to ensure observability.
Read-only
Self-clearing
16.13
TXI_DEL
Transmit FIFO has detected movement toward overflow which should result in an automatic
deletion. Event is latched to ensure observability. This is not an indication of an error.
Read-only
Self-clearing
16.12
TXI_INS
Transmit FIFO has detected movement toward underflow which should result in an automatic
insertion. Event is latched to ensure observability. This is not an indication of an error.
Read-only
Self-clearing
16.11:10
Reserved
First read always returns 01. Subsequent reads are indeterminate.
Read-only
Self-clearing
16.9:0
NOTE: Power-on reset value: 0x0400.
Reserved
Read returns 0.
Read-only
Table 9. Receiver Status Bit Definitioins (Register 17)
BIT(S)
NAME
DESCRIPTION
READ/WRITE
17.15
RXO_OVFL
Receive FIFO has detected an overflow error. Event is latched to ensure observability.
Read-only
Self-clearing
17.14
RXO_UNFL
Receive FIFO has detected an underflow error. Event is latched to ensure observability.
Read-only
Self-clearing
17.13
RXO_DEL
Receive FIFO has detected movement toward overflow which should result in an automatic
deletion. Event is latched to ensure observability. This is not an indication of an error.
Read-only
Self-clearing
17.12
RXO_INS
Receive FIFO has detected movement toward underflow which should result in an
automatic insertion. Event is latched to ensure observability. This is not an indication of an
error.
Read-only
Self-clearing
17.11:10
Reserved
First read always returns 01. Subsequent reads are indeterminate
Read-only
Self-clearing
17.9
RXG_HIBER_SAV
64/66b bit error rate (BER > 10E
–
4). The occurrence of this condition does not cause the
receive state machine to transition to the RX_INIT state and it does not output line fault
characters on the XGMII receive interface.
Frame-sync BER count. Contains the value from the most recent 250-
μ
s count period.
Changes automatically once every 250
μ
s
Read-only
Self-clearing
17.8:1
RXG_ERR_CNT
Read-only
Self-clearing
17.0
NOTE: Power-on reset value: 0x0400.
Reserved
Read returns 0.
Read-only