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參數(shù)資料
| 型號： | DLKPC192S |
| 英文描述： | 10Gbps Ethernet LAN Physical Coding Sublayer (PCS) Device |
| 中文描述： | 10Gbps的以太網(wǎng)物理編碼子層（PCS）設(shè)備 |
| 文件頁數(shù)： | 4/25頁 |
| 文件大小： | 360K |
| 代理商： | DLKPC192S |
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SLLS536
–
AUGUST 2002
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Signal Terminal Functions
XGMII interface terminals
SIGNAL
LOCATION
TYPE
DESCRIPTION
TC
E9
SSTL class 2,
2.5-V input
XGMII transmit clock. The XGMII transmit data on TD[0:31] and control word generator
signals on KG[0:3] are latched on the rising and falling edges of TC.
TD[0:31]
C14, B14, A14, D14,
E13, A13, C13, D12,
C12, A12, B12, E12,
E11, E10, D10, C10,
A10, B10, D9, B9,
C9, E8, E7, C7,
B7, A7, D7, E6,
C6, A6, C5, B5
SSTL class 2,
2.5-V input
XGMII transmit data. The data on this bus is latched on the rising and falling edges of
TC.
KG[0:3]
A5, D5, B4, A4
SSTL class 2,
2.5-V input
XGMII transmit control word. The control signals on these terminals are used to
designate whether the data on the TD bus is data characters or protocol control
characters. When high, these terminals cause the data on corresponding byte of the
TD bus to be interpreted as control characters by the PCS. The assignment of control
bits on this bus to corresponding bytes of the TD bus is as follows:
KG0
–
TD[0:7]
KG1
–
TD[8:15]
KG2
–
TD[16:23]
KG3
–
TD[24:31]
The value of these signals is latched on the rising and falling edge of TC.
RC
J5
SSTL class 2,
2.5-V output
XGMII receive clock. The received data and the control word generator signals are
transferred across the XGMII bus on RD[0:31] and KF[0:3], respectively, on the rising
and falling edges of RC. RC is generated from the input reference clock RFCP/RFCN.
RD[0:31]
C2, C1, D3, D2,
D1, E5, E4, E3,
F5, F2, F1, G5,
G4, G3, G1, H5,
H4, H3, J2, J1,
K5, K4, K3, K1,
K2, L5, L4, L3,
M2, M1, M5, N4
SSTL class 2,
2.5-V output
XGMII receive data. Parallel data on this bus is output on the rising and falling edges
of RC.
KF[0:3]
N1, N2, N3, P1
SSTL class 2,
2.5-V output
XGMII receive control word. The control signals on these terminals are used to
designate whether the data on the RD bus is data characters or protocol control
characters. When high, these terminals indicate the data on corresponding byte of the
RD bus is protocol control characters. The assignment of control bits on this bus to
corresponding bytes of the RD bus is as follows:
KF0
–
RD[0:7]
KF1
–
RD[8:15]
KF2
–
RD[16:23]
KF3
–
RD[24:31]
Data on these terminals is valid on the rising and falling edges of RC.
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| DLKPC192SGNT | 功能描述:IC ETHERNET LAN PCS 289-PBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| DLL-048R-2.14G | 制造商:MERRIMAC 制造商全稱:MERRIMAC 功能描述:DELAY LINE |
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| DLL-095R-2.14G | 制造商:MERRIMAC 制造商全稱:MERRIMAC 功能描述:DELAY LINE |
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