
DS3112
2 of 135
TABLE OF CONTENTS
1. INTRODUCTION ................................................................................................................................4
2.
SIGNAL
DESCRIPTION
..................................................................................................................
11
2.1 OVERVIEW/SIGNAL PIN LIST...................................................................................................11
2.2 CPU BUS SIGNAL DESCRIPTION..............................................................................................17
2.3 T3/E3 RECEIVE FRAMER SIGNAL DESCRIPTION.................................................................19
2.4 T3/E3 TRANSMIT FORMATTER SIGNAL DESCRIPTION......................................................21
2.5 LOW SPEED (T1 OR E1) RECEIVE PORT SIGNAL DESCRIPTION.......................................23
2.6 LOW SPEED (T1 OR E1) TRANSMIT PORT SIGNAL DESCRIPTION...................................24
2.7 HIGH SPEED (T3 OR E3) RECEIVE PORT SIGNAL DESCRIPTION......................................26
2.8 HIGH SPEED (T3 OR E3) TRANSMIT PORT SIGNAL DESCRIPTION..................................26
2.9 JTAG SIGNAL DESCRIPTION.....................................................................................................27
2.10 SUPPLY, TEST, RESET, AND MODE SIGNAL DESCRIPTION............................................27
3. MEMORY
MAP.................................................................................................................................29
4. MASTER DEVICE CONFIGURATION AND STATUS/INTERRUPT......................................31
4.1 MASTER RESET AND ID REGISTER DESCRIPTION..............................................................31
4.2 MASTER CONFIGURATION REGISTERS DESCRIPTION......................................................32
4.3 MASTER STATUS AND INTERRUPT REGISTER DESCRIPTION.........................................37
4.4 TEST REGISTER DESCRIPTION................................................................................................46
5. T3/E3 FRAMER .................................................................................................................................47
5.1 GENERAL DESCRIPTION...........................................................................................................47
5.2 T3/E3 FRAMER CONTROL REGISTER DESCRIPTION...........................................................48
5.3 T3/E3 FRAMER STATUS AND INTERRUPT REGISTER DESCRIPTION..............................53
5.4 T3/E3 PERFORMANCE ERROR COUNTERS ............................................................................60
6. M13/E13/G.747 MULTIPLEXER AND T2/E2/G.747 FRAMER..................................................64
6.1 GENERAL DESCRIPTION...........................................................................................................64
6.2 T2/E2/G.747 FRAMER CONTROL REGISTER DESCRIPTION................................................64
6.3 T2/E2/G.747 FRAMER STATUS AND INTERRUPT REGISTER DESCRIPTION...................66
6.4 T1/E1 AIS GENERATION CONTROL REGISTER DESCRIPTION..........................................70
7. T1/E1 LOOPBACK AND DROP AND INSERT FUNCTIONALITY.........................................73
7.1 GENERAL DESCRIPTION...........................................................................................................73
7.2 T1/E1 LOOPBACK CONTROL REGISTER DESCRIPTION......................................................74
7.3 T1 LINE LOOPBACK COMMAND STATUS REGISTER DESCRIPTION..............................78
7.4 T1/E1 DROP AND INSERT CONTROL REGISTER DESCRIPTION........................................79
8. BERT...................................................................................................................................................81
8.1 GENERAL DESCRIPTION...........................................................................................................81
8.2 BERT REGISTER DESCRIPTION................................................................................................81