參數(shù)資料
型號: DS3112N
英文描述: RECT BRIDGE GPP 15A 600V GBJ
中文描述: 坦佩化T3/E3復用器3.3化T3/E3成幀器和M13/E13/G.747復用器
文件頁數(shù): 67/135頁
文件大小: 585K
代理商: DS3112N
DS3112
67 of 135
T2E2SR1 STATUS BIT FLOW
Figure 6.3A
Internal LOF
Signal from
T2/E2 Framer 1
Note:
All event and alarm latches above are cleared when the T2E2SR1 register is read.
Register Name:
T2E2SR2
Register Description:
T2/E2 Status Register 2
Register Address:
36h
Bit #
7
6
5
Name
IERAI
RAI7
RAI6
Default
0
-
-
Bit #
15
14
13
Name
E2SOF4
E2SOF3
E2SOF2
Default
-
-
-
Note:
See Figure 6.3B for details on the signal flow for the status bits in the T2E2SR2 register.
Bits that are underlined are read-only; all other bits are read-write.
4
3
2
1
0
RAI5
-
RAI4
-
RAI3
-
RAI2
-
RAI1
-
12
11
10
9
8
E2SOF1
-
E2Sn4
-
E2Sn3
-
E2Sn2
-
E2Sn1
-
Alarm Latch
Change in State Detect
LOF1
(T2E2SR1
Bit 0)
Alarm Latch
Change in State Detect
Internal LOF
Signal from
T2/E2 Framer 2
Alarm Latch
Change in State Detect
Internal LOF
Signal from
T2 Framer 7
OR
Mask
IELOF
(T2E2SR1
Bit 7)
OR
LOF2
(T2E2SR1
Bit 1)
LOF7
(T2E2SR1
Bit 6)
Alarm Latch
Change in State Detect
AIS1
(T2E2SR1
Bit 8)
Internal AIS
Signal from
T2/E2 Framer 1
Alarm Latch
Change in State Detect
Internal AIS
Signal from
T2/E2 Framer 2
Alarm Latch
Change in State Detect
Internal AIS
Signal from
T2 Framer 7
OR
Mask
IEAIS
(T2E2SR1
Bit 15)
AIS2
(T2E2SR1
Bit 9)
AIS7
(T2E2SR1
Bit 14)
Mask
T2E2SR1
(IMSR Bit 5)
INT*
Hardware
Signal
T2E2SR1
Status Bit
(MSR Bit 5)
Event
Latch
Event
Latch
Event
Latch
Event
Latch
Event
Latch
Event
Latch
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