參數(shù)資料
型號: DS3112N
英文描述: RECT BRIDGE GPP 15A 600V GBJ
中文描述: 坦佩化T3/E3復(fù)用器3.3化T3/E3成幀器和M13/E13/G.747復(fù)用器
文件頁數(shù): 62/135頁
文件大?。?/td> 585K
代理商: DS3112N
DS3112
62 of 135
When the FECR is configured to count LOF occurrences, the FECR increments by one each time the
device loses receive synchronization. When the FECR is configured to count framing bit errors, it can be
configured via the ECC control bit in the T3/E3 Control Register (Section 5.2) to either continue counting
frame bit errors during a LOF or not.
Register Name:
PCR
Register Description:
T3 Parity Bit Error Count Register
Register Address:
26h
Bit #
7
6
5
4
Name
PE7
PE6
PE5
PE4
Default
-
-
-
-
Bit #
15
14
13
12
Name
PE15
PE14
PE13
PE12
Default
-
-
-
-
Note:
Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15/16-Bit T3 Parity Bit Error Counter (PE0 to PE15).
These bits report the number of T3
parity bit errors. In the E3 mode, this counter is meaningless and should be ignored. A parity bit error is
defined as an occurrence when the two parity bits do not match one another or when the two Parity Bits
do not match the parity calculation made on the information bits. Via the ECC control bit in the T3/E3
Control Register (Section 5.2), the PCR can be configured to either continue counting parity bit errors
during a LOF or not.
Register Name:
CPCR
Register Description:
T3 C-Bit Parity Bit Error Count Register
Register Address:
28h
Bit #
7
6
5
4
Name
CPE7
CPE6
CPE5
CPE4
Default
-
-
-
-
Bit #
15
14
13
12
Name
CPE15
CPE14
CPE13
CPE12
Default
-
-
-
-
Note:
Bits that are underlined are read-only; all other bits are read-write.
3
2
1
0
PE3
-
PE2
-
PE1
-
PE0
-
11
PE11
-
10
PE10
-
9
8
PE9
-
PE8
-
3
2
1
0
CPE3
-
CPE2
-
CPE1
-
CPE0
-
11
10
9
8
CPE11
-
CPE10
-
CPE9
-
CPE8
-
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