參數(shù)資料
型號: DS3112N
英文描述: RECT BRIDGE GPP 15A 600V GBJ
中文描述: 坦佩化T3/E3復(fù)用器3.3化T3/E3成幀器和M13/E13/G.747復(fù)用器
文件頁數(shù): 49/135頁
文件大?。?/td> 585K
代理商: DS3112N
DS3112
49 of 135
Bit 5/Transmit T3 Idle Signal Enable (T3IDLE).
When this bit is set high, the T3 Idle Signal will be
transmitted instead of the normal transmit data. The T3 Idle Signal is defined as a normally T3 framed
pattern (i.e., with the proper F bits and M bits along with the proper P bits) where the information bit
fields are completely filled with a data pattern of ...1100... and the C bits in Subframe 3 are set to zero and
both X bits are set to one. This bit is ignored in the E3 mode.
0 = transmit data normally
1 = transmit T3 Idle Signal
Bit 6/T3/E3 Line Loopback Enable (LLB).
See Figures 1A and 1B for a visual description of this
loopback.
0 = disable loopback
1 = enable loopback
Bit 7/T3/E3 Diagnostic Loopback Enable (DLB).
See Figures 1A and 1B for a visual description of this
loopback.
0 = disable loopback
1 = enable loopback
Bit 8/E3 Code Violation Enable (E3CVE).
This bit is ignored in the T3 mode. This bit is used in the E3
mode to configure the BiPolar Violation Count Register (BPVCR) to count either BiPolar Violations
(BPV) or Code Violations (CV). A BPV is defined as consecutive pulses (or marks) of the same polarity
that are not part of a HDB3 code word. A CV is defined in ITU O.161 as consecutive BPVs of the same
polarity.
0 = count BPV
1 = count CV
Bits 9 and 10/T3/E3 Frame Error Counting Control Bits 0 and 1 (FECC0 and FECC1).
FECC1
FECC0
FRAME ERROR COUNT REGISTER (FECR) CONFIGURATION
T3 Mode:
Count Loss Of Frame (LOF) Occurrences
E3 Mode:
Count Loss Of Frame (LOF) Occurrences
T3 Mode:
Count Both F Bit and M Bit Errors
E3 Mode:
Count Bit Errors in the FAS Word
T3 Mode:
Count Only F Bit Errors
E3 Mode:
Count Word Errors in the FAS Word
T3 Mode:
Count Only M Bit Errors
E3 Mode:
Illegal State
0
0
0
1
1
0
1
1
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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DS3112ND1E 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述:
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