參數(shù)資料
型號: DS3112N
英文描述: RECT BRIDGE GPP 15A 600V GBJ
中文描述: 坦佩化T3/E3復用器3.3化T3/E3成幀器和M13/E13/G.747復用器
文件頁數(shù): 85/135頁
文件大?。?/td> 585K
代理商: DS3112N
DS3112
85 of 135
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note:
Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Transmit Pattern Load (TC).
A low to high transition loads the pattern generator with Repetitive
or Pseudorandom pattern that is to be generated. This bit should be toggled from low to high whenever
the host wishes to load a new pattern. Must be cleared and set again for a subsequent loads.
Bit 4/Single Bit Error Insert (SBE).
A low to high transition will create a single bit error. Must be
cleared and set again for a subsequent bit error to be inserted.
Bits 5 to 7/Error Insert Bits (EIB0 to EIB2).
Will automatically insert bit errors at the prescribed rate into the generated data pattern. Useful for
verifying error detection operation.
EIB2
EIB1
EIB0
ERROR RATE INSERTED
0
0
0
No errors automatically inserted
0
0
1
10
-1
(1 error per 10 bits)
0
1
0
10
-2
(1 error per 100 bits)
0
1
1
10
-3
(1 error per 1kbits)
1
0
0
10
-4
(1 error per 10kbits)
1
0
1
10
-5
(1 error per 100kbits)
1
1
0
10
-6
(1 error per 1M bits)
1
1
1
10
-7
(1 error per 10M bits)
Bits 8 to 15/Alternating Word Count Rate (AWC0 to AWC7).
When the BERT is programmed in the
alternating word mode, the word in BERTRP0 will be transmitted for the count loaded into this register
plus one, then flip to the other word loaded in BERTRP1 and again repeat for the same number of times.
The valid count range is from 00h to FFh.
BERTC1
BERT Control Register 1
72h
7
6
5
4
3
2
1
0
EIB2
-
EIB1
0
EIB0
0
SBE
0
n/a
0
n/a
0
n/a
0
TC
0
15
14
13
12
11
10
9
8
AWC7
0
AWC6
0
AWC5
0
AWC4
0
AWC3
0
AWC2
0
AWC1
0
AWC0
0
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相關代理商/技術參數(shù)
參數(shù)描述
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