參數(shù)資料
型號(hào): DS3112N
英文描述: RECT BRIDGE GPP 15A 600V GBJ
中文描述: 坦佩化T3/E3復(fù)用器3.3化T3/E3成幀器和M13/E13/G.747復(fù)用器
文件頁數(shù): 61/135頁
文件大?。?/td> 585K
代理商: DS3112N
DS3112
61 of 135
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note:
Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15/16-Bit EXcessive Zero Counter (EXZ0 to EXZ15).
These bits report the number of
EXcessive Zero occurrences (EXZ). An EXZ occurrence is defined as three or more consecutive zeros in
the T3 mode and four or more consecutive zeros in the E3 mode. As an example, a string of eight
consecutive zeros would only increment this counter once.
Register Name:
FECR
Register Description:
Frame Error Count Register
Register Address:
24h
Bit #
7
6
5
4
Name
FE7
FE6
FE5
FE4
Default
-
-
-
-
Bit #
15
14
13
12
Name
FE15
FE14
FE13
FE12
Default
-
-
-
-
Note
: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15 / 16-Bit Framing Bit Error Counter (FE0 to FE15).
These bits report either the number of
Loss Of Frame (LOF) occurrences or the number of framing bit errors received. The FECR is configured
via the host by the Frame Error Counting Control Bits (FECC0 and FECC1) in the T3E3 Control Register
(Section 5.2). The possible configurations are shown below.
FRAME ERROR COUNT REGISTER (FECR)
EXZCR
EXcessive Zero Count Register
22h
7
6
5
4
3
2
1
0
EXZ7
-
EXZ6
-
EXZ5
-
EXZ4
-
EXZ3
-
EXZ2
-
EXZ1
-
EXZ0
-
15
14
13
12
11
10
9
8
EXZ15
-
EXZ14
-
EXZ13
-
EXZ12
-
EXZ11
-
EXZ10
-
EXZ9
-
EXZ8
-
3
2
1
0
FE3
-
FE2
-
FE1
-
FE0
-
11
FE11
-
10
FE10
-
9
8
FE9
-
FE8
-
FECC1
FECC0
CONFIGURATION
0
0
T3 Mode:
Count Loss Of Frame (LOF) Occurrences
E3 Mode:
Count Loss Of Frame (LOF) Occurrences
T3 Mode:
Count both F Bit and M Bit Errors
E3 Mode:
Count Bit Errors in the FAS Word
T3 Mode:
Count Only F Bit Errors
E3 Mode:
Count Word Errors in the FAS Word
T3 Mode:
Count only M Bit Errors
E3 Mode:
Illegal State
0
1
1
0
1
1
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