參數(shù)資料
型號： DS3112N
英文描述： RECT BRIDGE GPP 15A 600V GBJ
中文描述： 坦佩化T3/E3復用器3.3化T3/E3成幀器和M13/E13/G.747復用器
文件頁數(shù)： 89/135頁
文件大?。?/td> 585K
代理商： DS3112N
DS3112
89 of 135
Bit 6/Receive All Ones (RA1).
A latched read-only alarm-status bit that is set when 31 consecutive ones
are received. Allowed to be cleared once a zero is received.
Bits 8 to 15/BERT 24-Bit Error Counter (BEC0 to BEC7).
Lower byte of the 24-bit counter. See the
BERTEC1 register description for details.
BERT STATUS BIT FLOW
Figure 8.2A
RLOS
(BERTEC0
Bit 4)
BERT
Note:
All event and alarm latches above are cleared when the BERTEC0 register is read.
Register Name:
BERTEC1
Register Description:
BERT 24-Bit Error Counter (upper)
Register Address:
7Eh
Bit #
7
6
5
Name
BEC15
BEC14
BEC13
Default
0
0
0
Bit #
15
14
13
Name
BEC23
BEC22
BEC21
Default
0
0
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15/BERT 24-Bit Error Counter (BEC8 to BEC23).
Upper two bytes of the 24-bit counter.
This 24-bit counter will increment for each data bit received in error. This counter is not disabled when
the receive BERT loses synchronization. This counter can be cleared by toggling the LC control bit in
BERTBC0. This counter saturates and will not rollover. Upon saturation, the BECO status bit in the
BERTEC0 register will be set. This error counter starts counting when the BERT goes into receive
synchronization (RLOS = 0 or SYNC = 1) and it will not stop counting when the BERT loses
synchronization. It is recommended that the host toggle the LC bit in BERTC0 register once the BERT
has synchronized and then toggle the LC bit again when the error checking period is complete. If the
device loses synchronization during this period, then the counting results are suspect.
4
3
2
1
0
BEC12
0
BEC11
0
BEC10
0
BEC9
0
BEC8
0
12
11
10
9
8
BEC20
0
BEC19
0
BEC18
0
BEC17
0
BEC16
0
Alarm Latch
Change in State Detect
Internal RLOS
Signal from
Event Latch
Internal Bit
Error Detected
Signal from
BERT
Event Latch
Internal Counter
Overflow
Signal from
BERT
OR
BED
(BERTEC0
Bit 3)
BECO or BBCO
(BERTEC0
Bits 1 & 2)
Mask
BERT
(IMSR Bit 2)
INT*
Hardware
Signal
BERT
Status Bit
(MSR Bit 2)
Mask
IESYNC (BERTC0 Bit 15)
Mask
Mask
IEBED (BERTC0 Bit 14)
IEOF (BERTC0 Bit 13)
Event Latch
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS3112N+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112N+W 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112NC1 制造商:Maxim Integrated Products 功能描述:T3 E3 MULTIPLEXER, 3.3V T3/E3 FRAMER AND M13/E13/G.747 MUX - Rail/Tube
DS3112ND1E 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述:
DS3112RD 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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