參數(shù)資料
型號： DS3112N
英文描述： RECT BRIDGE GPP 15A 600V GBJ
中文描述： 坦佩化T3/E3復(fù)用器3.3化T3/E3成幀器和M13/E13/G.747復(fù)用器
文件頁數(shù)： 31/135頁
文件大?。?/td> 585K
代理商： DS3112N
DS3112
31 of 135
4. MASTER DEVICE CONFIGURATION AND STATUS/INTERRUPT
4.1 Master Reset and ID Register Description
The master reset and ID (MRID) register can be used to globally reset the device. When the RST bit is set
to one, all of the internal registers will be placed into their default state, which is 0000h. A reset can also
be invoked by the RST* hardware signal.
The upper byte of the MRID register is read-only and it can be read by the host to determine the chip
revision. Contact the factory for specifics on the meaning of the value read from the ID0 to ID7 bits.
Register Name:
MRID
Register Description:
Master Reset and ID Register
Register Address:
00h
Bit #
7
6
5
4
Name
n/a
n/a
n/a
n/a
Default
-
-
-
-
Bit #
15
14
13
12
Name
ID7
ID6
ID5
ID4
Default
X
X
X
X
Note:
Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Master Software Reset (RST).
When this bit is set to a one by the host, it will force all of the
internal registers to their default state, which is 0000h and forces the T3/E3 and T1/E1 outputs to send an
all ones pattern. This bit must be set high for a minimum of 100ns. This software bit is logically OR’ed
with the hardware signal RST*.
0 = normal operation
1 = force all internal registers to their default value of 0000h
Bit 1/Low Speed (T1/E1) Receive FIFO Reset (RFIFOR).
A zero to one transition on this bit will
cause the receive T1/E1 demux FIFOs to be reset, which will cause them to be flushed. See the DS3112
Block Diagrams in Figures 1A and 1B for details on the placement of the FIFOs within the chip. This bit
must be cleared and set again for a subsequent reset to occur.
Bit 2/T2/E2/G.747 Force Receive Framer Resynchronization (T2E2RSY).
A zero to one transition on
this bit will cause all seven of the T2 receive framers or all four of the E2 receive framers or all seven of
the G.747 framers to resynchronize. This bit must be cleared and set again for a subsequent
resynchronization to occur.
3
2
1
0
T3E3RSY
0
T2E2RSY
0
RFIFOR
0
RST
0
11
ID3
X
10
ID2
X
9
8
ID1
X
ID0
X
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS3112N+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112N+W 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112NC1 制造商:Maxim Integrated Products 功能描述:T3 E3 MULTIPLEXER, 3.3V T3/E3 FRAMER AND M13/E13/G.747 MUX - Rail/Tube
DS3112ND1E 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述:
DS3112RD 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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