參數(shù)資料
型號: DS3112N
英文描述: RECT BRIDGE GPP 15A 600V GBJ
中文描述: 坦佩化T3/E3復用器3.3化T3/E3成幀器和M13/E13/G.747復用器
文件頁數(shù): 59/135頁
文件大小: 585K
代理商: DS3112N
DS3112
59 of 135
Bit 2/F Bit or FAS Error Detected (FBE).
This latched read-only status bit will be set to a one when
the DS3112 has detected an error in either the F bits (T3 mode) or the FAS word (E3 mode). This bit will
be cleared when read and will not be set again until the device detects another error.
Bit 3/M Bit Error Detected (MBE).
This latched read-only event status bit will be set to a one when the
DS3112 has detected an error in the M bits. This bit will be cleared when read and will not be set again
until the device detects another error in one of the M bits. This status bit has no meaning in the E3 mode
and should be ignored.
Bit 4/EXcessive Zeros Detected (EXZ).
This latched read-only event status bit will be set to a one each
time the DS3112 has detected a consecutive string of either three or more zeros (T3 mode) or four or
more zeros (E3 mode). This bit will be cleared when read and will not be set again until the device detects
another EXcessive Zero event.
Bit 5/Severely Errored Framing Event Detected (SEFE).
This latched read-only event-status bit will
be set to a one each time the DS3112 has detected either three or more F bits in error out of 16
consecutive F bits (T3 mode) or four bad FAS words in a row (E3 mode). This bit will be cleared when
read and will not be set again until the device detects another SEFE event.
Bit 8/E3 National Bit (E3Sn).
This read-only real-time status bit reports the incoming E3 National Bit
(Sn). It is loaded at the start of each E3 frame as the Sn bit is decoded. The host can use the RSOF status
bit in the T3/E3 Status Register (T3E3SR) to determine when to read this bit.
Bit 9/T3 Application ID Channel Status (T3AIC).
This read-only real-time status bit can be used to
help determine whether an incoming T3 data stream is in C-Bit Parity mode or M23 mode. In C-Bit
Parity mode, it is recommended that the first C bit in each M frame be set to one. In M23 mode, the first
C bit in each M frame should be toggling between zero and one to indicate that the bits need to be stuffed
or not. This bit will be set to a one when the device detects that the first C bit in the M frame is set to one
for 1020 times or more out of 1024 consecutive M frames (109ms). It will be allowed to be cleared when
the device detects that the first C bit is set to one less than 1020 times out of 1024 consecutive M frames
(109ms). This status bit has no meaning in the E3 mode and should be ignored.
Bit10/Loss Of Signal Clear Detected (LOSC).
This latched read-only event-status bit will be set to a
one each time the T3/E3 framer exits a Loss Of Signal (LOS) state. This bit will be cleared when read and
will not be set again until the device once again exits the LOS state. The LOS alarm criteria is described
in Tables 5.3A and 5.3B. This status bit is useful in helping the host determine if the LOS persists as
defined in ANSI T1.231.
Bit11/Loss Of Frame Clear Detected (LOFC).
This latched read-only event-status bit will be set to a
one each time the T3/E3 framer exits a Loss Of Frame (LOF) state. This bit will be cleared when read and
will not be set again until the device once again exits the LOF state. The LOF alarm criteria is described
in Tables 5.3A and 5.3B. This status bit is useful in helping the host determine if the LOF persists as
defined in ANSI T1.231.
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相關代理商/技術參數(shù)
參數(shù)描述
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