參數(shù)資料
型號: DS3112N
英文描述: RECT BRIDGE GPP 15A 600V GBJ
中文描述: 坦佩化T3/E3復(fù)用器3.3化T3/E3成幀器和M13/E13/G.747復(fù)用器
文件頁數(shù): 30/135頁
文件大?。?/td> 585K
代理商: DS3112N
DS3112
SECTION
7.3
7.3
7.4
7.4
*
*
*
*
*
8.2
8.2
8.2
8.2
8.2
8.2
8.2
8.2
8.2
9.2
9.2
9.2
9.3
9.3
*
*
*
10.2
10.3
*
*
*
*
*
*
30 of 135
ADDRESS ACRONYM
5C
5E
60
62
64
66
68
6A
6C
6E
70
72
74
76
78
7A
7C
7E
80
82
84
86
88
8A
8C
8E
90
92
94
96
98
9A
9C
9E
*
Addresses A0 to FF are not assigned.
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R/W
R
W
R
R/W
R/W
R
REGISTER NAME
T1LBSR1
T1LBSR2
T1E1SDP
T1E1SIP
BERTMC
BERTC0
BERTC1
BERTRP0
BERTRP1
BERTBC0
BERTBC1
BERTEC0
BERTEC1
HCR
RHDLC
THDLC
HSR
IHSR
FCR
FSR
T1 Line Loopback Status Register 1.
T1 Line Loopback Status Register 2.
T1/E1 Select Register for Receive Drop Ports A and B.
T1/E1 Select Register for Transmit Drop Ports A and B.
Not Assigned
Not Assigned
Not Assigned
Not Assigned
Not Assigned
BERT Mux Control Register.
BERT Control 0.
BERT Control 1.
BERT Repetitive Pattern Set 0 (lower word).
BERT Repetitive Pattern Set 1 (upper word).
BERT Bit Counter 0 (lower word).
BERT Bit Counter 1 (upper word).
BERT Error Counter 0 (lower word).
BERT Error Counter 1 (upper word).
HDLC Control Register.
Receive HDLC FIFO Register.
Transmit HDLC FIFO Register.
HDLC Status Register.
Interrupt Mask Register for HSR.
Not Assigned
Not Assigned
Not Assigned
FEAC Control Register.
FEAC Status Register.
Not Assigned
Not Assigned
Not Assigned
Not Assigned
Not Assigned
Not Assigned
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