參數(shù)資料
型號： DS3112RD
廠商： Maxim Integrated Products, Inc.
英文描述： RECT BRIDGE GPP 15A 800V GBJ
中文描述： DS3/E3多路復(fù)用器參考設(shè)計
文件頁數(shù)： 101/135頁
文件大?。?/td> 585K
代理商： DS3112RD
DS3112
101 of 135
Bits 0 to 5/Transmit FEAC Code Word A Data (TFCA0 to TFCA5).
The FEAC code word is of the
form ...0xxxxxx011111111... where the rightmost bit is transmitted first. These six bits are the middle six
bits of the second byte of the FEAC code word (i.e., the six “x” bits). The device can generate two
different code words and these six bits represent what will be transmitted for code word A. TFCA0 is the
LSB and is transmitted first while TFCA5 is the MSB and is transmitted last. The TFS0 and TFS1 control
bits determine if this code word is to be generated. These bits should only be changed when the transmit
FEAC controller is in the idle state (TFS0 = 0 and TFS1 = 0).
Bits 6 and 7/Transmit FEAC Code Word Select Bits 0 and 1 (TFS0 and TFS1).
These two bits
control what two available code words should be generated. Both TFS0 and TFS1 are edge triggered. To
change the action, the host must go back to the null state (TFS0 = TFS1 = 0) before proceeding to the
desired action. Wait a minimum of (10) code words before changing to out-of-idle state.
TFS1
TFS0
0
0
Idle state; do not generate a FEAC code word (send all ones)
0
1
Send 10 of code word A followed by all ones
1
0
Send 10 of code word A followed by 10 of code word B followed by all ones
1
1
Send code word A continuously (will be sent for at least 10 times)
Bits 8 to 13/Transmit FEAC Code Word B Data (TFCB0 to TFCB5).
The FEAC code word is of the
form ...0xxxxxx011111111... where the rightmost bit is transmitted first. These six bits are the middle six
bits of the second byte of the FEAC code word (i.e., the six “x” bits). The device can generate two
different code words and these six bits represent what will be transmitted for code word B. TFCB0 is the
LSB and is transmitted first while TFCB5 is the MSB and is transmitted last. The TFS0 and TFS1 control
bits determine if this code word is to be generated. These bits should only be changed when the transmit
FEAC controller is in the idle state (TFS0 = 0 and TFS1 = 0).
Bit 14/Interrupt Enable, Receive FEAC Idle (IERFI).
This bit masks or enables interrupts caused by
the Receive FEAC Idle (RFI) bit in the FSR register.
0 = interrupt masked
1 = interrupt unmasked
Bit 15/Receive FEAC Controller Reset (RFR).
A zero to one transition will reset the receive FEAC
controller and flush the Receive FEAC FIFO. This bit must be cleared and set again for a subsequent
reset.
ACTION
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