- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376976 > DS3112RD (Maxim Integrated Products, Inc.) RECT BRIDGE GPP 15A 800V GBJ PDF資料下載
參數(shù)資料
| 型號： | DS3112RD |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | RECT BRIDGE GPP 15A 800V GBJ |
| 中文描述： | DS3/E3多路復(fù)用器參考設(shè)計 |
| 文件頁數(shù)： | 96/135頁 |
| 文件大?。?/td> | 585K |
| 代理商： | DS3112RD |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁當前第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁
DS3112
96 of 135
Bit 0/Transmit Packet End (TEND).
This latched read-only event-status bit will be set to a one each
time the transmit HDLC controller reads a transmit FIFO byte with the corresponding TMEND bit set or
if a FIFO underrun occurs. This bit will be cleared when read and will not be set again until another
message end is detected. The setting of this bit can cause a hardware interrupt to occur if the TEND bit in
the Interrupt Mask for HSR (IHSR) register is set to a one and the HDLC bit in the Interrupt Mask for
MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read.
Bit 2/Transmit FIFO Low Watermark (TLWM).
This read-only real time status bit will be set to a
one when the transmit FIFO contains less than the number of bytes configured by the Transmit Low
Watermark Setting control bits (TLWMS0 to TLWMS2) in the HDLC Control Register (HCR). This bit
will be cleared when the FIFO fills beyond the low watermark. The setting of this bit can cause a
hardware interrupt to occur if the TLWM bit in the Interrupt Mask for HSR (IHSR) register is set to a one
and the HDLC bit in the Interrupt Mask for MSR (IMSR) register is set to a one.
Bit 4/Receive FIFO High Watermark (RHWM).
This read-only real-time status bit will be set to a one
when the receive FIFO contains more than the number of bytes configured by the Receive High
Watermark Setting control bits (RHWMS0 to RHWMS2) in the HDLC Control Register (HCR). This bit
will be cleared when the FIFO empties below the high watermark. The setting of this bit can cause a
hardware interrupt to occur if the RHWM bit in the Interrupt Mask for HSR (IHSR) register is set to a
one and the HDLC bit in the Interrupt Mask for MSR (IMSR) register is set to a one.
Bit 5/Receive Packet Start (RPS).
This latched read-only event-status bit will be set to a one each time
the HDLC controller detects an opening byte of an HDLC packet. This bit will be cleared when read and
will not be set again until another message is detected. The setting of this bit can cause a hardware
interrupt to occur if the RPS bit in the Interrupt Mask for HSR (IHSR) register is set to a one and the
HDLC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to
clear when this bit is read.
Bit 6/Receive Packet End (RPE).
This latched read-only event-status bit will be set to a one each time
the HDLC controller detects the finish of a message whether the packet is valid (CRC correct) or not (bad
CRC, abort sequence detected, packet too small, not an integral number of octets, or an overrun
occurred). This bit will be cleared when read and will not be set again until another message end is
detected. The setting of this bit can cause a hardware interrupt to occur if the RPE bit in the Interrupt
Mask for HSR (IHSR) register is set to a one and the HDLC bit in the Interrupt Mask for MSR (IMSR)
register is set to a one. The interrupt will be allowed to clear when this bit is read.
Bit 7/Transmit FIFO Underrun (TUDR).
This latched read-only event-status bit will be set to a one
each time the transmit FIFO underruns and an abort is automatically sent. This bit will be cleared when
read and will not be set again until another underrun occurs (i.e., the FIFO has been written to and then
allowed to empty again). The setting of this bit can cause a hardware interrupt to occur if the TUDR bit in
the Interrupt Mask for HSR (IHSR) register is set to a one and the HDLC bit in the Interrupt Mask for
MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read.
Bits 8 to 11/Transmit FIFO Level Bits 0 to 3 (TFL0 to TFL3).
These read-only real-time status bits
indicate the current depth of the transmit FIFO with a 16-byte resolution. These status bits cannot cause a
hardware interrupt.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS3134 | Chateau Channelized T1 And E1 And HDLC Controller |
| DS3160 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| DS3171 | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
| DS3171N | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
| DS3172 | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3116MP000 | 制造商:Thomas & Betts 功能描述:MAXGARD - RR8F |
| DS311X | 功能描述:KWIK-CHG DESIGNATION STRIPS DBL RoHS:是 類別:盒，外殼，支架 >> 插線臺，插座面板 - 配件 系列:Kwik-Change® 標準包裝:50 系列:- 附件類型:模擬插頭，雙 樣式:耳機，0.173" 直徑 包括:- |
| DS312 | 功能描述:插線板 DESIGN STRIP COVER RoHS:否 制造商:Switchcraft 產(chǎn)品類型:Bantam (TT) 正規(guī)化: 高度/機架數(shù)量: 深度: 端接類型: 位置/觸點數(shù)量:48 |
| DS-312 | 制造商:MA-COM 制造商全稱:M/A-COM Technology Solutions, Inc. 功能描述:Four-Way Power Divider, 10 - 500 MHz |
| DS312_09 | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3E FPGA Family: Introduction and Ordering Information |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。