參數(shù)資料
型號： DS3112RD
廠商： Maxim Integrated Products, Inc.
英文描述： RECT BRIDGE GPP 15A 800V GBJ
中文描述： DS3/E3多路復(fù)用器參考設(shè)計
文件頁數(shù)： 34/135頁
文件大?。?/td> 585K
代理商： DS3112RD
DS3112
34 of 135
Bit 7/T3/E3 Transmit Frame Sync I/O Control (FTSOFC).
When this bit is set low, the FTSOF signal
will be an output and will pulse for one FTCLK cycle at the beginning of each frame. When this bit is
high, the FTSOF signal is an input and the device uses it to determine the frame boundaries.
0 = FTSOF is an output
1 = FTSOF is an input
Bit 8/Low-Speed (T1/E1) Transmit Port Common Clock Enable (LTCCEN).
When this bit is set
high, the LTCLK1 to LTCLK28 and LTCLKA and LTCLKB inputs are ignored and a common clock
sourced via the LTCCLK input is used in their place.
0 = disable LTCCLK
1 = enable LTCCLK
Bit 9/Low-Speed (T1/E1) Receive Port Common Clock Enable (LRCCEN).
When this bit is set high,
the LRCLK1 to LRCLK28 and LRCLKA and LRCLKB outputs will all be sourced from the LRCCLK
input. This configuration can only be used in applications where it can be insured that all of the T1 or E1
channels from the far end are being sourced from a common clock.
0 = disable LRCCLK
1 = enable LRCCLK
Bit 10/High-Speed (T3/E3) Data Enable Mode Select (DENMS).
When this bit is set low, the FRDEN
and FTDEN outputs will be asserted during payload data and deasserted during overhead data. When this
bit is high, FRDEN and FTDEN are gapped clocks that pulse during payload data and are suppressed
during overhead data.
0 = FRDEN and FTDEN are data enables
1 = FRDEN and FTDEN are gapped clocks
Bit 11/Low-Speed (T1/E1) Port Loop Timed Mode (LLTM).
When this bit is set low, the low speed
T1 and E1 receive clocks (LRCLK) are not routed to the transmit side. When this bit is high, the LRCLKs
are routed to the transmit side to be used as the transmit T1 and E1 clocks. When enabled, all the low
speed ports are looped timed. This control bit affects all the low speed ports. The device is not capable of
setting individual low speed ports into and out of looped timed mode. See the block diagram in Figures
1A and 1B for more details.
0 = disable loop timed mode (LRCLK is not used to replace the associated LTCLK)
1 = enable loop timed mode (LRCLK replaces the associated LTCLK)
Register Name:
MC2
Register Description:
Master Configuration Register 2
Register Address:
04h
Bit #
7
6
5
4
Name
n/a
n/a
HTDATL
HTDATH
Default
-
-
0
0
Bit #
15
14
13
12
Name
n/a
n/a
n/a
n/a
Default
-
-
-
-
3
2
1
0
HRDATI HRCLKI HTDATI HTCLKI
0
0
0
0
11
10
9
8
LRDATI LRCLKI
0
LTDATI
0
LTCLKI
0
0
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