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| 型號(hào)： | DS3112RD |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | RECT BRIDGE GPP 15A 800V GBJ |
| 中文描述： | DS3/E3多路復(fù)用器參考設(shè)計(jì) |
| 文件頁(yè)數(shù)： | 51/135頁(yè) |
| 文件大?。?/td> | 585K |
| 代理商： | DS3112RD |
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DS3112
51 of 135
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note:
Bits that are underlined are read-only; all other bits are read-write.
Bit 0/BiPolar Violation Insert (BPVI).
A zero to one transition on this bit will cause a single BPV to be
inserted into the transmit data stream. Once this bit has been toggled from a 0 to a 1, the device waits for
the next occurrence of three consecutive ones to insert the BPV. This bit must be cleared and set again for
a subsequent error to be inserted. Toggling this bit has no affect when the T3/E3 interface is in the
Unipolar Mode (Section 4.2 for details about the Unipolar Mode). In the manual error insert mode
(MEIMS = 1), errors will be inserted on each toggle of the FTMEI input signal as long as this bit is set
high. When this bit is set low, no errors will be inserted.
Bit 1/EXcessive Zero Insert (EXZI).
A zero to one transition on this bit will cause a single EXZ event
to be inserted into the transmit data stream. An EXZ event is defined as three or more consecutive zeros
in the T3 mode and four or more consecutive zeros in the E3 mode. Once this bit has been toggled from a
zero to a one, the device waits for the next possible B3ZS/HDB3 code word insertion and it suppresses
that code word from being inserted and hence this creates the EXZ event. This bit must be cleared and set
again for a subsequent error to be inserted. Toggling this bit has no affect when the T3/E3 interface is in
the Unipolar Mode (Section 4.2 for details about the Unipolar Mode). In the Manual Error Insert mode
(MEIMS = 1), errors will be inserted on each toggle of the FTMEI input signal as long as this bit is set
high. When this bit is set low, no errors will be inserted.
Bit 2/T3 Parity Bit Error Insert (T3PBEI).
A zero to one transition on this bit will cause a single T3
parity error event to be inserted into the transmit data stream. A T3 parity event is defined as flipping the
proper polarity of both the P bits in a T3 Frame. (See Section 15.2 for details about the P bits.) Once this
bit has been toggled from a zero to a one, the device waits for the next T3 frame to flip both P bits. This
bit must be cleared and set again for a subsequent error to be inserted. Toggling this bit has no affect
when the device is operated in the E3 mode. In the Manual Error Insert mode (MEIMS = 1), errors will
be inserted on each toggle of the FTMEI input signal as long as this bit is set high. When this bit is set
low, no errors will be inserted.
T3E3EIC
T3/E3 Error Insert Control Register
18h
7
6
5
4
3
2
1
0
MEIMS
0
FBEIC1
0
FBEIC0
0
FBEI
0
T3CPBEI
0
T3PBEI
0
EXZI
0
BPVI
0
15
n/a
-
14
n/a
-
13
n/a
-
12
n/a
-
11
n/a
-
10
n/a
-
9
8
n/a
-
n/a
-
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