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| 型號(hào)： | DS3112RD |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | RECT BRIDGE GPP 15A 800V GBJ |
| 中文描述： | DS3/E3多路復(fù)用器參考設(shè)計(jì) |
| 文件頁(yè)數(shù)： | 70/135頁(yè) |
| 文件大?。?/td> | 585K |
| 代理商： | DS3112RD |
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DS3112
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6.4 T1/E1 AIS Generation Control Register Description
Via the T1/E1 Alarm Indication Signal (AIS) Control Registers, the host can configure the DS3112 to
generate an unframed all ones signal in either the transmit or receive paths on the 28 T1 ports or the 16/21
E1 ports. On reset, the device will force AIS in both the transmit and receive paths and it is up to the host
to modify the T1/E1 AIS Generation Control Registers to allow normal T1/E1 traffic to traverse the
DS3112. See the block diagrams in Section 1 for details on where the AIS signal is injected into the data
flow. When the M13/E13 multiplexer function is disabled in the DS3112 (see the UNCHEN control bit
in the Master Control Register 1 in Section 4.2 for details), the T1/E1 AIS Generation Control Registers
are meaningless and can be set to any value.
Register Name:
T1E1RAIS1
Register Description:
T1/E1 Receive Path AIS Generation Control Register 1
Register Address:
40h
Bit #
7
6
5
4
Name
AIS8
AIS7
AIS6
AIS5
Default
0
0
0
0
Bit #
15
14
13
12
Name
AIS16
AIS15
AIS14
AIS13
Default
0
0
0
0
Note
:
Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15/Receive AIS Generation Control for T1/E1 Ports 1 to 16 (AIS1 to AIS2).
These bits
determine whether the device will replace the demultiplexed T1/E1 data stream with an unframed all ones
AIS signal. AIS1 controls the data at LRDAT1, AIS2 controls the data at LRDAT2, and so on. Since
ports 4, 8, 12, 16, 20, 24, and 28 are not active in the G.747 mode, the AIS4, AIS8, AIS12, and AIS16
bits have no affect in the G.747 mode.
0 = send AIS to the LRDAT output
1 = send normal data to the LRDAT output
Register Name:
T1E1RAIS2
Register Description:
T1/E1 Receive Path AIS Generation Control Register 2
Register Address:
42h
Bit #
7
6
5
4
Name
AIS24
AIS23
AIS22
AIS21
Default
0
0
0
0
Bit #
15
14
13
12
Name
n/a
n/a
n/a
n/a
Default
-
-
-
-
Note:
Bits that are underlined are read-only; all other bits are read-write.
3
2
1
0
AIS4
0
AIS3
0
AIS2
0
AIS1
0
11
10
9
8
AIS12
0
AIS11
0
AIS10
0
AIS9
0
3
2
1
0
AIS20
0
AIS19
0
AIS18
0
AIS17
0
11
10
9
8
AIS28
0
AIS27
0
AIS26
0
AIS25
0
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