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| 型號(hào)： | DS3112RD |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | RECT BRIDGE GPP 15A 800V GBJ |
| 中文描述： | DS3/E3多路復(fù)用器參考設(shè)計(jì) |
| 文件頁(yè)數(shù)： | 102/135頁(yè) |
| 文件大?。?/td> | 585K |
| 代理商： | DS3112RD |
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DS3112
102 of 135
10.3 FEAC Status Register Description
Register Name:
Register Description:
Register Address:
Bit #
7
Name
n/a
n/a
Default
-
Bit #
15
14
Name
RFFO
RFFE
Default
-
Note:
Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Receive FEAC Code Word Detected (RFCD).
This latched read-only event-status bit will be set
to a one each time the FEAC controller has detected and validated a new FEAC code word. This bit will
be cleared when read and will not be set again until another new code word is detected. The setting of this
bit can cause a hardware interrupt to occur if the FEAC bit in the Interrupt Mask for MSR (IMSR)
register is set to a one. The interrupt will be allowed to clear when this bit is read.
Bit 1/Receive FEAC Idle (RFI).
This latched read-only event status bit will be set to a one each time the
FEAC controller has detected 16 consecutive ones following a valid code word. This bit will be cleared
when read. The setting of this bit can cause a hardware interrupt to occur if the IERFI bit in the FEAC
Control Register (FCR) is set to one and the FEAC bit in the Interrupt Mask for MSR (IMSR) is set to
one.
Bits 8 to 13/Receive FEAC FIFO Data (RFF0 to RFF5).
Data from the Receive FEAC FIFO can be
read from these bits. The FEAC code word is of the form ...0xxxxxx011111111... where the rightmost bit
is received first. These six bits are the debounced and integrated middle six bits of the second byte of the
FEAC code word (i.e., the six “x” bits). RFF0 is the LSB and is received first while RFF5 is the MSB and
is received last.
Bit 14/Receive FEAC FIFO Empty (RFFE).
This read-only real time status bit will be set to a one
when the Receive FEAC FIFO is empty and hence the RFF0 to RFF5 bits contain no valid information.
This latched read-only event-status bit will be set to a
one when the receive FEAC controller has attempted to write to an already full Receive FEAC FIFO and
current incoming FEAC code word is lost. This bit will be cleared when read and will not be set again
until another FIFO overflow occurs (i.e., the Receive FEAC FIFO has been read and then fills beyond
capacity).
FSR
FEAC Status Register
92h
6
5
4
3
2
1
0
n/a
-
n/a
-
n/a
-
n/a
-
RFI
-
RFCD
-
-
13
12
11
10
9
8
RFF5
-
RFF4
-
RFF3
-
RFF2
-
RFF1
-
RFF0
-
-
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