1056
SAM4CP [DATASHEET]
43051E–ATPL–08/14
50.
Revision History
In the table that follow, the most recent version of the document appears first.
Doc. Rev.
43051
Comments
Change
Request
Ref.
E
Minor Changes.
‘SCLK’ replaced by ‘SLCK’ in all document.
Power Supply and Power Control
Modified
Section 5.1.2 “LCD Voltage Regulator” on page 14
.
Modified
Section 5.1.4 “Automatic Power Switch” on page 14
.
Modified
Section 5.1.5 “Typical Powering Schematics” on page 14
.
Added
Section 5.1.5.2 “Single Supply with Backup Battery” on page 16
.
Modified
Section 5.1.5.3 “Single Power Supply using One Main Battery and LCD Controller in
Backup Mode” on page 17
.
Updated
Section 5.3.2 “Device Configuration after a Power Cycle when Booting from Flash
Memory” on page 20
and
Section 5.3.3 “Device Configuration after a Reset” on page 20
.
Input/Output Lines
Updated
Section 6.9 “ERASE Pin” on page 28
.
Memories
Updated
Section 8.1.4.5 “Security Bit Feature” on page 35
.
Added
Section 8.1.5.4 “Sub-system 1 Start-up Time” on page 37
System Controller
Updated
Section 10.2.4 “Supply Monitor on VDDIO” on page 41
.
Peripherals
Table 11-4, “I/O Line Features Abbreviations”
: removed Medium Drive. Added Maximum
Drive.
Table 11-5, “Multiplexing on PIO Controller A (PIOA)”
,
Table 11-6, “Multiplexing on PIO
Controller B (PIOB)”
,
Table 11-7, “Multiplexing on PIO Controller C (PIOC)”
: modified
Features column in all tables for all I/O lines.
ARM Cortex-M4 Processor
Corrected instruction in
Section 12.5.3 “Power Management Programming Hints” on page 79
.
Updated
Table 12-5, “Memory Region Shareability Policies”
Updated
Table 12-11, “Faults”
Updated
Table 12-31, “Mapping of Interrupts to the Interrupt Variables”
Updated
Table 12-41, “Memory Protection Unit (MPU) Register Mapping”
with new register
names for MPU_RBAR_Ax and MPU_RASR_Ax.
Section 12.9.1.13 “Configurable Fault Status Register” on page 207
added LSPERR bit.
SAM4CP Boot Program
Section 14.5.3 “In Application Programming (IAP) Feature” on page 266
: corrected MC_FSR
to EEFC_FSR.