172
SAM4CP [DATASHEET]
43051E–ATPL–08/14
12.6.11.27 VSTM
Floating-point Store Multiple.
Syntax
VSTM{
mode
}{
cond
}{.
size
}
Rn
{
!
},
list
where:
mode
is the addressing mode:
- IA
Increment After. The consecutive addresses start at the address specified in
Rn
. This is the default
and can be omitted.
- DB
Decrement Before. The consecutive addresses end just before the address specified in
Rn
.
cond
is an optional condition code, see
“Conditional Execution”
.
size
is an optional data size specifier.
If present, it must be equal to the size in bits, 32 or 64, of the registers in
list
.
Rn
is the base register. The SP can be used.
!
is the function that causes the instruction to write a modified value back to
Rn
.
Required if mode == DB.
list
is a list of the extension registers to be stored, as a list of consecutively numbered doubleword or single-
word registers, separated by commas and surrounded by brackets.
Operation
This instruction:
Stores multiple extension registers to consecutive memory locations using a base address from an ARM
core register.
Restrictions
The restrictions are:
List must contain at least one register.
If it contains doubleword registers it must not contain more than 16 registers.
Use of the PC as
Rn
is deprecated.
Condition Flags
These instructions do not change the flags.
12.6.11.28 VSTR
Floating-point Store.
Syntax
VSTR{
cond
}{.
32
}
Sd
, [
Rn
{, #
imm
}]
VSTR{
cond
}{.
64
}
Dd
, [
Rn
{, #
imm
}]
where
cond
is an optional condition code, see
“Conditional Execution”
.
32, 64
are the optional data size specifiers.
Sd
is the source register for a singleword store.
Dd
is the source register for a doubleword store.
Rn
is the base register. The SP can be used.
imm
is the + or - immediate offset used to form the address. Values are multiples of 4 in the range 0-1020.
imm
can be omitted, meaning an offset of +0.