
647
SAM4CP [DATASHEET]
43051E–ATPL–08/14
33.5
Signal Description
33.6
Product Dependencies
33.6.1 I/O Lines
The pins used for interfacing the compliant external devices can be multiplexed with PIO lines. The programmer must
first program the PIO controllers to assign the SPI pins to their peripheral functions.
33.6.2 Power Management
The SPI can be clocked through the Power Management Controller (PMC), thus the programmer must first configure the
PMC to enable the SPI clock.
33.6.3 Interrupt
The SPI interface has an interrupt line connected to the interrupt controller. Handling the SPI interrupt requires
programming the interrupt controller before configuring the SPI.
33.6.4 Peripheral DMA Controller (PDC)
The SPI interface can be used in conjunction with the PDC in order to reduce processor overhead. For a full description
of the PDC, refer to the corresponding section in the full datasheet.
Table 33-1. Signal Description
Pin Name
Pin Description
Type
Master
Slave
MISO
Master In Slave Out
Input
Output
MOSI
Master Out Slave In
Output
Input
SPCK
Serial Clock
Output
Input
NPCS1 - NPCS3
Peripheral Chip Selects
Output
Unused
NPCS0/NSS
Peripheral Chip Select/Slave Select
Output
Input
Table 33-2.
I/O Lines
Instance
Signal
I/O Line
Peripheral
SPI1
SPI1_MISO
PC3
A
SPI1
SPI1_MOSI
PC4
A
SPI1
SPI1_NPCS0
PC2
A
SPI1
SPI1_NPCS1
PC6
B
SPI1
SPI1_NPCS2
PC7
B
SPI1
SPI1_NPCS3
PC8
B
SPI1
SPI1_SPCK
PC5
A
Table 33-3.
Peripheral IDs
Instance
ID
SPI1
40