
752
SAM4CP [DATASHEET]
43051E–ATPL–08/14
Figure 36-17. ASK Modulator Output
Figure 36-18. FSK Modulator Output
36.6.3.6 Synchronous Receiver
In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the baud rate clock. If a
low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver
waits for the next start bit. Synchronous mode operations provide a high speed transfer capability.
Configuration fields and bits are the same as in asynchronous mode.
Figure 36-19
illustrates a character reception in synchronous mode.
Figure 36-19. Synchronous Mode Character Reception
36.6.3.7 Receiver Operations
When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit
in US_CSR rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last
character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing a 1 to the
RSTSTA (Reset Status) bit in the US_CR.
Manchester
encoded
data
default polarity
unipolar output
Txd
ASK Modulator
Output
Uptstream Frequency F0
NRZ stream
1
0
0
1
Manchester
encoded
data
default polarity
unipolar output
FSK Modulator
Txd
Output
Uptstream Frequencies
[F0, F0+offset]
NRZ stream
1
0
0
1
D0
D1
D2
D3
D4
D5
D6
D7
RXD
Start
Sampling
Parity Bit
Stop Bit
Example: 8-bit, Parity Enabled 1 Stop
Baud Rate
Clock