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型號(hào)：	E5550F-DOW
廠商：	TEMIC SEMICONDUCTORS
元件分類：	通信及網(wǎng)絡(luò)
英文描述：	SPECIALTY TELECOM CIRCUIT, UUC7
封裝：	DIE-7
文件頁(yè)數(shù)：	543/1069頁(yè)
文件大?。?/td>	14303K
代理商：	E5550F-DOW

SAM4CP [DATASHEET]

43051E–ATPL–08/14

Select the Programmable Clocks:

Programmable clocks are controlled via registers, PMC_SCER, PMC_SCDR and PMC_SCSR.

Programmable clocks can be enabled and/or disabled via PMC_SCER and PMC_SCDR. Three programmable

clocks can be used. PMC_SCSR indicates which Programmable clock is enabled. By default all Programmable

clocks are disabled.

PMC_PCKx registers are used to configure Programmable clocks.

The CSS field is used to select the Programmable clock divider source. Several clock options are available: main

clock, slow clock, PLLACK, PLLBCK. The slow clock is the default clock source.

The PRES field is used to control the Programmable clock prescaler. It is possible to choose between different

values (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler input divided by PRES parameter. By

default, the PRES value is set to 0 which means that PCKx is equal to slow clock.

Once PMC_PCKx register has been configured, the corresponding Programmable clock must be enabled and the

user is constrained to wait for the PCKRDYx bit to be set in the PMC_SR. This can be done either by polling

PCKRDYx in PMC_SR or by waiting for the interrupt line to be raised if the associated interrupt source

(PCKRDYx) has been enabled in PMC_IER. All parameters in PMC_PCKx can be programmed in a single write

If the CSS and PRES parameters are to be modified, the corresponding Programmable clock must be disabled

first. The parameters can then be modified. Once this has been done, the user must re-enable the Programmable

clock and wait for the PCKRDYx bit to be set.

Enable the Peripheral Clocks:

Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via

registers PMC_PCER0, PMC_PCER, PMC_PCDR0 and PMC_PCDR.

30.16 Clock Switching Details

30.16.1 Master Clock Switching Timings

and give the worst case timings required for the Master Clock to switch from one selected clock to another

one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock

cycles of the newly selected clock has to be added.

PLL designates either the PLLA or the PLLB Clock.

PLLCOUNT designates either PLLACOUNT or PLLBCOUNT.

Clock Switching Timings (Worst Case)

2.5 x Main Clock

3 x PLL Clock +

1 x Main Clock

0.5 x Main Clock +

3 x PLL Clock +

0.5 x Main Clock +

PLLCOUNT x SLCK +

2.5 x PLLx Clock

2.5 x PLL Clock +

PLLCOUNT x SLCK

2.5 x PLL Clock +

PLLCOUNT x SLCK

相關(guān)PDF資料	PDF描述
E5551A-DIT	SPECIALTY TELECOM CIRCUIT, UUC7
E5551A-DOW	SPECIALTY TELECOM CIRCUIT, UUC7
E5551A-FP008	SPECIALTY TELECOM CIRCUIT, PDSO8
E5551A-FP008	SPECIALTY TELECOM CIRCUIT, PDSO8
E5551A-DOW	SPECIALTY TELECOM CIRCUIT, UUC7

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
E5550F-S8	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder
E5551A-DIT	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder
E5551A-DOW	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder
E5551A-FP008	制造商:未知廠家制造商全稱:未知廠家功能描述:TRANSPONDER\|CMOS\|SOP\|8PIN\|PLASTIC
E5552	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder

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