328
SAM4CP [DATASHEET]
43051E–ATPL–08/14
characteristics section. In order to set the bypass mode, the OSCBYPASS bit of the Supply Controller Mode register
(SUPC_MR) must be set at 1.
20.4.3 Core Voltage Regulator Control/Backup Low-Power Mode
The Supply Controller can be used to control the embedded voltage regulator.
The voltage regulator automatically adapts its quiescent current depending on the required load current. More
information can be found in the Electrical Characteristics section.
The user can switch off the voltage regulator, and thus put the device in backup mode, by writing SUPC_CR with the
VROFF bit at 1.
This asserts the system reset signal after the write resynchronization time which lasts two slow clock cycles (worst case).
Once the system reset signal is asserted, the processor and the peripherals are stopped one slow clock cycle before
shutting down the core voltage regulator and pulling the SHDN pin to ground.
When the user does not use the internal voltage regulator and wants to supply VDDCORE by an external supply, it is
possible to disable the voltage regulator. This is done through ONREG bit in SUPC_MR.
20.4.4 LCD Voltage Regulator Control
The Supply Controller can be used to select the power supply source of the LCD voltage regulator.
This selection is done by the LCDMODE field in SUPC_MR. After a backup reset, the LCDMODE field is at 0x0. No
power supply source is selected and the SLCD Controller reset signal is asserted.
The status of the LCD Controller reset is given by the LCDS field in SUPC_ SR.
If LCDMODE is written to 0x2 while it is at 0x0, after the write resynchronization time (about 2 slow clock cycles),
the external power supply source is selected, then after one slow clock cycle, the SLCDC reset signal is released.
If LCDMODE is written to 0x0 while it is at 0x2, after the write resynchronization time (about 2 slow clock cycles),
the SLCDC reset signal is asserted, then after one slow clock cycle, the external power supply source is
deselected.
If LCDMODE is written to 0x3 while it is at 0x0, after the write resynchronization time (about 2 slow clock cycles),
the internal power supply source is selected and the embedded regulator is turned on, then after 15 slow clock
cycles, the SLCDC reset signal is released.
If LCDMODE is written to 0x0 while it is at 0x3, after the write resynchronization time (about 2 slow clock cycles),
the SLCDC reset signal, then after one slow clock cycle, the internal power supply source is deselected.
There are several restrictions concerning the write of the LCDMODE field:
The user must check that the previous power supply selection is done before writing LCDMODE again. To do that,
the user must check that the LCDS flag has the correct value. If LCDMODE is written to 0x0, the LCDS flag is reset
at 0. If LCDMODE is written to 0x0, the LCDS flag is set at 1.
Writing LCDMODE to 0x2 while it is at 0x3 or writing LCDMODE to 0x3 while it is at 0x2 is forbidden and has no
effect.
Before writing LCDMODE to 0x2, the user must ensure that the external power supply is ready and supplies the
VDDLCD pin.
Before writing LCDMODE to 0x3, the user must ensure that the external power supply does not supply the
VDDLCD pin.
To use the LCD controller to maintain display in backup mode, all configuration registers must be kept when backup
mode entered.
20.4.5 Using Backup Battery/Automatic Power Switch
The power switch is able to automatically select one power source among VDDBU and VDDIO.
As soon as VDDIO is present (higher than 1.9V), it supplies the backup area of the device (VDDBU_SW = VDDIO) even
if the voltage of VDDBU is higher than VDDIO. If not, the backup area is supplied by the VDDBU voltage source
(VDDBU_SW = VDDBU). For more information about power supply schematics, refer to the section on Power
Considerations.