国产毛片a,久久大香伊蕉在人线观看热vr

您現(xiàn)在的位置：買賣IC網 > PDF目錄358702 > E5550F-DOW (TEMIC SEMICONDUCTORS) SPECIALTY TELECOM CIRCUIT, UUC7 PDF資料下載

型號：	E5550F-DOW
廠商：	TEMIC SEMICONDUCTORS
元件分類：	通信及網絡
英文描述：	SPECIALTY TELECOM CIRCUIT, UUC7
封裝：	DIE-7
文件頁數(shù)：	803/1069頁
文件大?。?/td>	14303K
代理商：	E5550F-DOW

SAM4CP [DATASHEET]

43051E–ATPL–08/14

Functional Description

37.6.1 TC Description

The three channels of the Timer Counter are independent and identical in operation except when quadrature decoder is

enabled. The registers for channel programming are listed in

Table 37-5 on page 822

37.6.2 16-bit Counter

Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the

selected clock. When the counter has reached the value 2

- 1 and passes to zero, an overflow occurs and the COVFS

bit in the TC Status Register (TC_SR) is set.

The current value of the counter is accessible in real time by reading the TC Counter Value Register (TC_CV). The

counter can be reset by a trigger. In this case, the counter value passes to zero on the next valid edge of the selected

37.6.3 Clock Selection

At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or

TCLK2, or be connected to the internal I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC Block

Mode Register (TC_BMR). See

Figure 37-2 ”Clock Chaining Selection”

Each channel can independently select an internal or external clock source for its counter:

Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4, TIMER_CLOCK5

External clock signals: XC0, XC1 or XC2

This selection is made by the TCCLKS bits in the TC Channel Mode Register (TC_CMR).

The selected clock can be inverted with the CLKI bit in the TC_CMR. This allows counting on the opposite edges of the

The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the

TC_CMR defines this signal (none, XC0, XC1, XC2). See

Figure 37-3 ”Clock Selection”

In all cases, if an external clock is used, the duration of each of its levels must be longer than the peripheral

clock period. The external clock frequency must be at least 2.5 times lower than the peripheral clock.

相關PDF資料	PDF描述
E5551A-DIT	SPECIALTY TELECOM CIRCUIT, UUC7
E5551A-DOW	SPECIALTY TELECOM CIRCUIT, UUC7
E5551A-FP008	SPECIALTY TELECOM CIRCUIT, PDSO8
E5551A-FP008	SPECIALTY TELECOM CIRCUIT, PDSO8
E5551A-DOW	SPECIALTY TELECOM CIRCUIT, UUC7

相關代理商/技術參數(shù)	參數(shù)描述
E5550F-S8	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder
E5551A-DIT	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder
E5551A-DOW	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder
E5551A-FP008	制造商:未知廠家制造商全稱:未知廠家功能描述:TRANSPONDER\|CMOS\|SOP\|8PIN\|PLASTIC
E5552	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder

發(fā)布緊急采購，3分鐘左右您將得到回復。

(若只采購一條型號，填寫一行即可)

*型號	*數(shù)量	廠商	批號	封裝