661
SAM4CP [DATASHEET]
43051E–ATPL–08/14
33.8.2 SPI Mode Register
Name:
SPI_MR
Address:
0x40008004 (0), 0x48000004 (1)
Access:
Read/Write
This register can only be written if the WPEN bit is cleared in
”SPI Write Protection Mode Register”
.
MSTR: Master/Slave Mode
0 = SPI is in Slave mode.
1 = SPI is in Master mode.
PS: Peripheral Select
0 = Fixed Peripheral Select.
1 = Variable Peripheral Select.
PCSDEC: Chip Select Decode
0 = The chip selects are directly connected to a peripheral device.
1 = The four chip select lines are connected to a 4- to 16-bit decoder.
When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit
decoder. The Chip Select Registers define the characteristics of the 15 chip selects, with the following rules:
SPI_CSR0 defines peripheral chip select signals 0 to 3.
SPI_CSR1 defines peripheral chip select signals 4 to 7.
SPI_CSR2 defines peripheral chip select signals 8 to 11.
SPI_CSR3 defines peripheral chip select signals 12 to 14.
MODFDIS: Mode Fault Detection
0 = Mode fault detection enabled.
1 = Mode fault detection disabled.
WDRBT: Wait Data Read Before Transfer
0 = No Effect. In master mode, a transfer can be initiated regardless of the SPI_RDR state.
1 = In Master Mode, a transfer can start only if the SPI_RDR is empty, i.e. does not contain any unread data. This mode prevents
overrun error in reception.
31
30
29
28
27
26
25
24
DLYBCS
23
–
22
–
21
–
20
–
19
18
17
16
PCS
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
6
–
5
4
3
–
2
1
0
LLB
WDRBT
MODFDIS
PCSDEC
PS
MSTR