
892
SAM4CP [DATASHEET]
43051E–ATPL–08/14
39.8.4 SLCDC Display Register
Name:
SLCDC_DR
Address:
0x4003C00C
Access:
Read/Write
Reset:
0x00000000
This register can only be written if the WPEN bit is cleared in the
“SLCDC Write Protection Mode Register”
.
DISPMODE: Display Mode Register
(Processed at beginning of next frame).
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
14
13
12
11
10
9
8
LCDBLKFREQ
7
–
6
–
5
–
4
–
3
–
2
1
0
DISPMODE
Value
Name
Description
0x0
NORMAL
Normal Mode:
Latched data are displayed.
0x1
FORCE_OFF
Force Off Mode:
All pixels are invisible. (The SLCDC memory is
unchanged).
0x2
FORCE_ON
Force On Mode:
All pixels are visible. (The SLCDC memory is unchanged).
0x3
BLINKING
Blinking Mode:
All pixels are alternately turned off to the predefined state
in SLCDC memory at LCDBLKFREQ frequency. (The
SLCDC memory is unchanged).
0x4
INVERTED
Inverted Mode:
All pixels are set in the inverted state as defined in SLCDC
memory. (The SLCDC memory is unchanged).
0x5
INVERTED_BLINK
Inverted Blinking Mode:
All pixels are alternately turned off to the predefined
opposite state in SLCDC memory at LCDBLKFREQ
frequency. (The SLCDC memory is unchanged).
0x6
USER_BUFFER_LOAD
User Buffer Only Load Mode:
Blocks the automatic transfer from User Buffer to Display
Buffer.
0x7
BUFFERS_SWAP
Buffer Swap Mode:
All pixels are alternatively assigned to the state defined in
the User Buffer, then to the state defined in the Display
Buffer at LCDBLKFREQ frequency.