941
SAM4CP [DATASHEET]
43051E–ATPL–08/14
41.
Advanced Encryption Standard (AES)
41.1
Description
The Advanced Encryption Standard (AES) is compliant with the American
FIPS (Federal Information Processing
Standard) Publication 197
specification.
The AES supports all five confidentiality modes of operation for symmetrical key block cipher algorithms (ECB, CBC,
OFB, CFB and CTR), as specified in the
NIST Special Publication 800-38A Recommendation,
as well as Galois/Counter
Mode (GCM) as specified in the
NIST Special Publication 800-38D Recommendation
.
It is compatible with all these
modes via Peripheral DMA Controller channels, minimizing processor intervention for large buffer transfers.
The 128-bit/192-bit/256-bit key is stored in four/six/eight 32-bit write-only AES Key Word Registers (AES_KEYWRx).
The 128-bit input data and initialization vector (for some modes) are each stored in four 32-bit write-only AES Input Data
Registers (AES_IDATARx) and AES Initialization Vector Registers (AES_IVRx).
As soon as the initialization vector, the input data and the key are configured, the encryption/decryption process may be
started. Then the encrypted/decrypted data are ready to be read out on the four 32-bit AES Output Data Registers
(AES_ODATARx) or through the PDC channels.
41.2
Embedded Characteristics
Compliant with
FIPS Publication 197, Advanced Encryption Standard (AES).
128-bit/192-bit/256-bit Cryptographic Key.
12/14/16 Clock Cycles Encryption/Decryption Processing Time with a 128-bit/192-bit/256-bit Cryptographic Key.
Double Input Buffer Optimizes Runtime.
Support of the Modes of Operation Specified in the
NIST Special Publication 800-38A and NIST Special
Publication 800-38D:
Electronic Code Book (ECB).
Cipher Block Chaining (CBC) including CBC-MAC.
Cipher Feedback (CFB).
Output Feedback (OFB).
Counter (CTR).
Galois/Counter Mode (GCM).
8-, 16-, 32-, 64- and 128-bit Data Sizes Possible in CFB Mode.
Last Output Data Mode Allows Optimized Message Authentication Code (MAC) Generation.
Connection to PDC Channel Capabilities Optimizes Data Transfers for all Operating Modes.
One Channel for the Receiver, One Channel for the Transmitter.
Next Buffer Support.
41.3
Product Dependencies
41.3.1 Power Management
The AES may be clocked through the Power Management Controller (PMC), so the programmer must first to configure
the PMC to enable the AES clock.
41.3.2 Interrupt
The AES interface has an interrupt line connected to the Interrupt Controller.
Handling the AES interrupt requires programming the Interrupt Controller before configuring the AES.