975
SAM4CP [DATASHEET]
43051E–ATPL–08/14
42.5
Functional Description
The Integrity Check Monitor (ICM) is a DMA controller that performs SHA-based memory hashing over memory regions.
As shown in
Figure 42-2
, it integrates a DMA interface, a Monitoring Finite State Machine (FSM), an integrity scheduler,
a set of context registers, a SHA engine, an APB interface and configuration registers.
When the ICM module is enabled, it sequentially retrieves a circular list of region descriptors from the memory (Main List
described in
Figure 42-3
). Up to four regions may be monitored. Each region descriptor is composed of four words
indicating the layout of the memory region (see
Figure 42-4
). It also contains the hashing engine configuration on a per
region basis. As soon as the descriptor is loaded from the memory and context registers are updated with the data
structure, the hashing operation starts. A programmable number of Blocks (see TRSIZE field of the ICM_RCTRL
structure member) is transferred from the memory to the SHA engine. When the desired number of blocks have been
transferred, the digest is whether moved to memory (write-back function) or compared with a digest reference located in
the system memory (compare function). If a digest mismatch occurs, an interrupt is triggered if unmasked. The ICM
module passes through the Region descriptor list until the end of the list marked by an End of List bit set to one. To
continuously monitor the list of regions, the WRAP bit must be set to one in the last data structure.
Figure 42-3.
ICM Region Descriptor and Hash Areas
Table 42-1.
Peripherals IDs
Instance
ID
ICM
34
ICM Descriptor
Area - Contiguous
Read-only Memory
Region 0
Descriptor
Region 1
Descriptor
Region N
Descriptor
Wrap=1
Wrap=0
Wrap=0
infinite loop
when wrap bit is set
End of Region 0
End of Region 1 List
End of Region N
Region 0 Hash
Region 1 Hash
Region N Hash
ICM Hash Area -
Contiguous
Read-write once
Memory
Main List
Secondary List