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型號(hào)：	EP1S30F780I6N
廠商：	Altera
文件頁(yè)數(shù)：	253/864頁(yè)
文件大?。?/td>	0K
描述：	IC STRATIX FPGA 30K LE 780-FBGA
產(chǎn)品培訓(xùn)模塊：	Three Reasons to Use FPGA's in Industrial Designs
產(chǎn)品變化通告：	Package Height Change 03/March/2008
標(biāo)準(zhǔn)包裝：	18
系列：	Stratix®
LAB/CLB數(shù)：	3247
邏輯元件/單元數(shù)：	32470
RAM 位總計(jì)：	3317184
輸入/輸出數(shù)：	597
電源電壓：	1.425 V ~ 1.575 V
安裝類(lèi)型：	表面貼裝
工作溫度：	-40°C ~ 100°C
封裝/外殼：	780-BBGA
供應(yīng)商設(shè)備封裝：	780-FBGA（29x29）

Altera Corporation

Stratix Device Handbook, Volume 2

July 2005

Enhanced PLLs

Programmable Duty Cycle

The programmable duty cycle allows enhanced PLLs to generate clock

outputs with a variable duty cycle. This feature is supported on each

enhanced PLL post-scale counter (g0..g3, l0..l3, e0..e3). The duty cycle

setting is achieved by a low and high time count setting for the post-scale

counters. The Quartus II software uses the frequency input and the

required multiply or divide rate to determine the duty cycle choices. The

precision of the duty cycle is determined by the post-scale counter value

chosen on an output. The precision is defined by 50% divided by the post-

scale counter value. The closest value to 100% is not achievable for a given

counter value. For example, if the g0 counter is 10, then steps of 5% are

possible for duty cycle choices between 5 to 90%.

If the device uses external feedback, you must set the duty cycle for the

counter driving off the device to 50%.

General Advanced Clear & Enable Control

There are several control signals for clearing and enabling PLLs and PLL

outputs. You can use these signals to control PLL resynchronization and

gate PLL output clocks for low-power applications.

The pllenable pin is a dedicated pin that enables/disables PLLs. When

the pllenable pin is low, the clock output ports are driven by GND and

all the PLLs go out of lock. When the pllenable pin goes high again, the

PLLs relock and resynchronize to the input clocks. You can choose which

PLLs are controlled by the pllenable signal by connecting the

input port of the altpll megafunction to the common

The areset signals are reset/resynchronization inputs for each PLL. The

signal should be asserted every time the PLL loses lock to

guarantee correct phase relationship between the PLL output clocks.

Users should include the areset signal in designs if any of the following

conditions are true:

PLL reconfiguration or clock switchover enables in the design

Phase relationships between output clocks need to be maintained

after a loss of lock condition

The device input pins or logic elements (LEs) can drive these input

signals. When driven high, the PLL counters reset, clearing the PLL

output and placing the PLL out of lock. The VCO sets back to its nominal

setting (~700 MHz). When driven low again, the PLL resynchronizes to

its input as it relocks. If the target VCO frequency is below this nominal

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