91亚洲精品高清久久久,热e国产%20热视频二区

您好，
買賣IC網(wǎng)歡迎您。
請(qǐng)登錄
免費(fèi)注冊(cè)

您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4338 > EP1S30F780I6N (Altera)IC STRATIX FPGA 30K LE 780-FBGA PDF資料下載

型號(hào)：	EP1S30F780I6N
廠商：	Altera
文件頁(yè)數(shù)：	62/864頁(yè)
文件大小：	0K
描述：	IC STRATIX FPGA 30K LE 780-FBGA
產(chǎn)品培訓(xùn)模塊：	Three Reasons to Use FPGA's in Industrial Designs
產(chǎn)品變化通告：	Package Height Change 03/March/2008
標(biāo)準(zhǔn)包裝：	18
系列：	Stratix®
LAB/CLB數(shù)：	3247
邏輯元件/單元數(shù)：	32470
RAM 位總計(jì)：	3317184
輸入/輸出數(shù)：	597
電源電壓：	1.425 V ~ 1.575 V
安裝類型：	表面貼裝
工作溫度：	-40°C ~ 100°C
封裝/外殼：	780-BBGA
供應(yīng)商設(shè)備封裝：	780-FBGA（29x29）

Altera Corporation

Stratix Device Handbook, Volume 1

July 2005

High-Speed Differential I/O Support

The output levels are compatible with systems of the same voltage as the

power supply (i.e., when VCCIO pins are connected to a 1.5-V power

supply, the output levels are compatible with 1.5-V systems). When

pins are connected to a 3.3-V power supply, the output high is

3.3 V and is compatible with 3.3-V or 5.0-V systems.

Table 2–36 summarizes Stratix MultiVolt I/O support.

High-Speed

Differential I/O

Stratix devices contain dedicated circuitry for supporting differential

standards at speeds up to 840 Mbps. The following differential I/O

standards are supported in the Stratix device: LVDS, LVPECL,

HyperTransport, and 3.3-V PCML.

There are four dedicated high-speed PLLs in the EP1S10 to EP1S25

devices and eight dedicated high-speed PLLs in the EP1S30 to EP1S80

devices to multiply reference clocks and drive high-speed differential

SERDES channels.

See the Stratix device pin-outs at www.altera.com for additional high

speed DIFFIO pin information for Stratix devices.

Table 2–36. Stratix MultiVolt I/O Support Note (1)

Input Signal (5)

Output Signal (6)

1.5 V1.8 V2.5 V3.3 V5.0 V1.5 V1.8 V2.5 V3.3 V5.0 V

Notes to Table 2–36:

To drive inputs higher than VCCIO but less than 4.1 V, disable the PCI clamping diode. However, to drive 5.0-V

inputs to the device, enable the PCI clamping diode to prevent VI from rising above 4.0 V.

The input pin current may be slightly higher than the typical value.

Although VCCIO specifies the voltage necessary for the Stratix device to drive out, a receiving device powered at a

different level can still interface with the Stratix device if it has inputs that tolerate the VCCIO value.

Stratix devices can be 5.0-V tolerant with the use of an external resistor and the internal PCI clamp diode.

This is the external signal that is driving the Stratix device.

This represents the system voltage that Stratix supports when a VCCIO pin is connected to a specific voltage level.

For example, when VCCIO is 3.3 V and if the I/O standard is LVTTL/LVCMOS, the output high of the signal

coming out from Stratix is 3.3 V and is compatible with 3.3-V or 5.0-V systems.

相關(guān)PDF資料	PDF描述
24LC02BT-I/MS	IC EEPROM 2KBIT 400KHZ 8MSOP
EP1S30F780C5N	IC STRATIX FPGA 30K LE 780-FBGA
24AA02T-I/MS	IC EEPROM 2KBIT 400KHZ 8MSOP
EP2SGX60EF1152I4N	IC STRATIX II GX 60K 1152-FBGA
ASM36DTBS	CONN EDGECARD 72POS R/A .156 SLD

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
EP1S-3G1	制造商:NEC 制造商全稱:NEC 功能描述:LOW SOUND PRESSURE
EP1S-3G1T	制造商:NEC 制造商全稱:NEC 功能描述:LOW SOUND PRESSURE
EP1S-3G1TT	制造商:NEC 制造商全稱:NEC 功能描述:LOW SOUND PRESSURE
EP1S-3G2	制造商:NEC 制造商全稱:NEC 功能描述:LOW SOUND PRESSURE
EP1S-3G2T	制造商:NEC 制造商全稱:NEC 功能描述:LOW SOUND PRESSURE

發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

(若只采購(gòu)一條型號(hào)，填寫一行即可)

*型號(hào)	*數(shù)量	廠商	批號(hào)	封裝

采購(gòu)需求

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

我的聯(lián)系方式

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)