11–40
Altera Corporation
Stratix Device Handbook, Volume 2
July 2005
Configuration Schemes
JTAG-chain device programming is ideal when the PCB contains multiple
devices, or when testing the PCB using JTAG BST circuitry.
Figure 11–21shows multi-device JTAG configuration.
Figure 11–21. Multi-Device JTAG Configuration Notes (1), (2) (1)
Stratix, Stratix GX, APEXTM II, APEX 20K, MercuryTM, ACEX 1K, and FLEX 10K devices can be placed within the
same JTAG chain for device programming and configuration.
(2)
(3)
Connect the nCONFIG, MSEL0, MSEL1, and MSEL2 pins to support a non-JTAG configuration scheme. If only JTAG
configuration is used, connect nCONFIG to VCC, and MSEL0, MSEL1, and MSEL2 to ground. Pull DATA0 and DCLK
to either high or low.
(4)
VIO is a reference voltage for the MasterBlaster output driver. VIO should match the device’s VCCIO. See the
MasterBlaster Serial/USB Communications Cable Data Sheet for this value.
(5)
nCE
must be connected to GND or driven low for successful JTAG configuration.
The nCE pin must be connected to GND or driven low during JTAG
configuration. In multi-device PS, FPP and PPA configuration chains, the
first device's nCE pin is connected to GND while its nCEO pin is connected
to nCE of the next device in the chain. The last device's nCE input comes
from the previous device, while its nCEO pin is left floating. After the first
device completes configuration in a multi-device configuration chain, its
nCEO
pin drives low to activate the second device's nCE pin, which
prompts the second device to begin configuration. Therefore, if these
devices are also in a JTAG chain, you should make sure the nCE pins are
connected to GND during JTAG configuration or that the devices are JTAG
configured in the same order as the configuration chain. As long as the
devices are JTAG configured in the same order as the multi-device
configuration chain, the nCEO of the previous device drives nCE of the
next device low when it has successfully been JTAG configured.
TMS
TCK
MasterBlaster or ByteBlasterMV
10-Pin Male Header
TDI
TDO
VCC
Pin 1
nSTATUS
nCONFIG
MSEL2
MSEL1
nCE
VCC
CONF_DONE
VCC
TMS
TCK
TDI
TDO
nCONFIG
MSEL2
MSEL1
nCE
VCC
CONF_DONE
VCC
TMS
TCK
TDI
TDO
nCONFIG
MSEL2
MSEL1
nCE
VCC
CONF_DONE
VCC
1 k
Ω
(3)
MSEL0
(3)
MSEL0
(3)
DCLK
(3)
DATA0
(3)
MSEL0
(3)
VIO
(4)
Stratix Device
1 k
Ω
nSTATUS
10 k
Ω
10 k
Ω
10 k
Ω
10 k
Ω
10 k
Ω
10 k
Ω
(5)
1 k
Ω