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型號(hào)：	EP1S30F780I6N
廠商：	Altera
文件頁(yè)數(shù)：	652/864頁(yè)
文件大?。?/td>	0K
描述：	IC STRATIX FPGA 30K LE 780-FBGA
產(chǎn)品培訓(xùn)模塊：	Three Reasons to Use FPGA's in Industrial Designs
產(chǎn)品變化通告：	Package Height Change 03/March/2008
標(biāo)準(zhǔn)包裝：	18
系列：	Stratix®
LAB/CLB數(shù)：	3247
邏輯元件/單元數(shù)：	32470
RAM 位總計(jì)：	3317184
輸入/輸出數(shù)：	597
電源電壓：	1.425 V ~ 1.575 V
安裝類(lèi)型：	表面貼裝
工作溫度：	-40°C ~ 100°C
封裝/外殼：	780-BBGA
供應(yīng)商設(shè)備封裝：	780-FBGA（29x29）

Altera Corporation

Stratix Device Handbook, Volume 2

July 2005

General Architecture

Logic Elements

Stratix and Stratix GX device LEs include several new, advanced features

that improve design performance and reduce logic resource consumption

(see Table 10–1). The Quartus II software automatically uses these new

LE features to improve device utilization.

In addition to the new LE features described in Table 10–1, there are

enhancements to the chains that connect LEs together. Carry chains are

implemented vertically in Stratix and Stratix GX devices, instead of

horizontally as in APEX II and APEX 20K devices, and continue across

rows, instead of across columns, as shown in Figure 10–1. Also note that

the Stratix and Stratix GX architectures do not support the cascade

primitive. Therefore, the Quartus II Compiler automatically converts

Table 10–1. Stratix & Stratix GX LE Features

Function

of an LE and the register input of an

adjacent LE within the same logic array

Conserves LE resources

Provides fast shift register

implementation

Saves local interconnect routing

resources within an LAB

Look-up table (LUT) chain

interconnects

Direct path between the combinatorial

output of an LE and the fast LUT input

of an adjacent LE within the same LAB

Allows LUTs within the same LAB to

cascade together for high-speed wide

fan-in functions, such as wide XOR

Bypasses local interconnect for

faster performance

Allows the register output to feed back

into the LUT of the same LE, such that

the register is packed with its own fan-

Enhanced register packing mode

Uses resources more efficiently

Dynamic arithmetic mode

Uses one set of LEs for implementing

both an adder and subtractor

Improves performance for functions

that switch between addition and

subtraction frequently, such as

Carry-select chain

Calculates outputs for a possible carry-

in of 1 or 0 in parallel

Gives immediate access to result for

both a carry-in of 1 or 0

Increases speed of carry functions

for high-speed operations, such as

counters, adders, and comparators

Asynchronous clear and

asynchronous preset

Supports direct asynchronous clear

and preset functions

Conserves LE resources

Does not require additional logic

resources to implement NOT-gate

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