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型號(hào)：	EP1S30F780I6N
廠商：	Altera
文件頁(yè)數(shù)：	416/864頁(yè)
文件大小：	0K
描述：	IC STRATIX FPGA 30K LE 780-FBGA
產(chǎn)品培訓(xùn)模塊：	Three Reasons to Use FPGA's in Industrial Designs
產(chǎn)品變化通告：	Package Height Change 03/March/2008
標(biāo)準(zhǔn)包裝：	18
系列：	Stratix®
LAB/CLB數(shù)：	3247
邏輯元件/單元數(shù)：	32470
RAM 位總計(jì)：	3317184
輸入/輸出數(shù)：	597
電源電壓：	1.425 V ~ 1.575 V
安裝類(lèi)型：	表面貼裝
工作溫度：	-40°C ~ 100°C
封裝/外殼：	780-BBGA
供應(yīng)商設(shè)備封裝：	780-FBGA（29x29）

Altera Corporation

July 2005

5. High-Speed Differential I/O

Interfaces in Stratix Devices

Introduction

To achieve high data transfer rates, Stratix devices support True-

LVDSTM differential I/O interfaces which have dedicated

serializer/deserializer (SERDES) circuitry for each differential I/O pair.

Stratix SERDES circuitry transmits and receives up to 840 megabits per

second (Mbps) per channel. The differential I/O interfaces in Stratix

devices support many high-speed I/O standards, such as LVDS,

LVPECL, PCML, and HyperTransportTM technology. Stratix device high-

speed modules are designed to provide solutions for many leading

protocols such as SPI-4 Phase 2, SFI-4, 10G Ethernet XSBI, RapidIO,

HyperTransport technology, and UTOPIA-4.

The SERDES transmitter is designed to serialize 4-, 7-, 8-, or 10-bit wide

words and transmit them across either a cable or printed circuit board

(PCB). The SERDES receiver takes the serialized data and reconstructs the

bits into a 4-, 7-, 8-, or 10-bit-wide parallel word. The SERDES contains the

necessary high-frequency circuitry, multiplexer, demultiplexer, clock,

and data manipulation circuitry. You can use double data rate I/O

(DDRIO) circuitry to transmit or receive differential data in by-one (

Contact Altera Applications for more information on other B

values that the Stratix devices support and using

×7-mode in the

Quartus II software. Stratix devices currently only support

B = 1 and B = 7 in

This chapter describes the high-speed differential I/O capabilities of

Stratix programmable logic devices (PLDs) and provides guidelines for

their optimal use. You should use this document in conjunction with the

Stratix Device Family Data Sheet section of the Stratix Device Handbook,

Volume 1. Consideration of the critical issues of controlled impedance of

traces and connectors, differential routing, termination techniques, and

DC balance gets the best performance from the device. Therefore, an

elementary knowledge of high-speed clock-forwarding techniques is also

Stratix I/O Banks

Stratix devices contain eight I/O banks, as shown in Figure 5–1. The two

I/O banks on each side contain circuitry to support high-speed LVDS,

LVPECL, PCML, HSTL Class I and II, SSTL-2 Class I and II, and

HyperTransport inputs and outputs.

S52005-3.2

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