Section I–6
Altera Corporation
Stratix Device Family Data Sheet
Stratix Device Handbook, Volume 1
4
updated table.
April 2004, v3.0
● The minimum and maximum duty cycle values in Note 3 of Table 4–8 ● Changes were made to values in SSTL-3 Class I and II rows in
● Changed Table 4–55 title from “EP1S10 Column Pin Fast Regional Clock External I/O Timing Parameters” to “EP1S10 External I/O
Timing on Column Pins Using Fast Regional Clock Networks.”
● Added tSU and tCO_C rows and made changes to values in tPRE and
tCLKHL rows in Table 4–46. ● Values changed in the tSU and tH rows in Table 4–47. ● Values changed in the tMRAMCLKHL row in Table 4–50. November 2003, v2.2
Chapter
Date/Version
Changes Made