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型號(hào)：	EP1S30F780I6N
廠商：	Altera
文件頁數(shù)：	417/864頁
文件大?。?/td>	0K
描述：	IC STRATIX FPGA 30K LE 780-FBGA
產(chǎn)品培訓(xùn)模塊：	Three Reasons to Use FPGA's in Industrial Designs
產(chǎn)品變化通告：	Package Height Change 03/March/2008
標(biāo)準(zhǔn)包裝：	18
系列：	Stratix®
LAB/CLB數(shù)：	3247
邏輯元件/單元數(shù)：	32470
RAM 位總計(jì)：	3317184
輸入/輸出數(shù)：	597
電源電壓：	1.425 V ~ 1.575 V
安裝類型：	表面貼裝
工作溫度：	-40°C ~ 100°C
封裝/外殼：	780-BBGA
供應(yīng)商設(shè)備封裝：	780-FBGA（29x29）

Altera Corporation

Stratix Device Handbook, Volume 2

July 2005

Stratix I/O Banks

Figure 5–1. Stratix I/O Banks Notes (1), (2), (3)

Notes to Figure 5–1:

Figure 5–1 is a top view of the Stratix silicon die, which corresponds to a top-down view of non-flip-chip packages

and a bottom-up view of flip-chip packages.

Figure 5–1 is a graphic representation only. See the pin list and the Quartus II software for exact locations.

Banks 9 through 12 are enhanced PLL external clock output banks.

If the high-speed differential I/O pins are not used for high-speed differential signaling, they can support all of the

I/O standards except HSTL Class I and II, GTL, SSTL-18 Class II, PCI, PCI-X 1.0, and AGP 1

pads five or more pads away from a differential pad. Use the Show Pads view in the Quartus II Floorplan Editor to

locate these pads. The Quartus II software gives an error message for illegal output or bidirectional pin placement

next to a high-speed differential I/O pin.

Stratix Differential I/O Standards

Stratix devices provide a multi-protocol interface that allows

communication between a variety of I/O standards, including LVDS,

HyperTransport technology, LVPECL, PCML, HSTL Class I and II, and

LVDS, LVPECL, 3.3-V PCML,

and HyperTransport I/O Block

and Regular I/O Pins (4)

LVDS, LVPECL, 3.3-V PCML,

and HyperTransport I/O Block

and Regular I/O Pins (4)

I/O Banks 3, 4, 9 & 10 Support

All Single-Ended I/O Standards

I/O Banks 7, 8, 11 & 12 Support

All Single-Ended I/O Standards

I/O Banks 1, 2, 5, and 6 Support All

Single-Ended I/O Standards Except

Differential HSTL Output Clocks,

Differential SSTL-2 Output Clocks,

HSTL Class II, GTL, SSTL-18 Class II,

PCI, PCI-X 1.0, and AGP 1

LVDS, LVPECL, 3.3-V PCML,

and HyperTransport I/O Block

and Regular I/O Pins (4)

LVDS, LVPECL, 3.3-V PCML,

and HyperTransport I/O Block

and Regular I/O Pins (4)

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