參數(shù)資料
型號: EWIXP460AC
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: 400 MHz, RISC PROCESSOR, PBGA544
封裝: LEAD FREE, PLASTIC, BGA-544
文件頁數(shù): 128/163頁
文件大?。?/td> 1123K
代理商: EWIXP460AC
Package Information
May 2005
Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet
67
Document Number: 306261-002
UTP_IP_ADDR[4:0]
Z
VO
O
Receive PHY address bus.
Used by the processor when operating in MPHY mode to poll and select a single PHY at any one
given time.
UTP_IP_FCO
Z
VO
TRI
UTOPIA Input Data Flow Control Output signal: Also known as the RX_ENB_N.
In SPHY configurations, UTP_IP_FCO is used to inform the PHY that the processor is ready to
accept data.
In MPHY configurations, UTP_IP_FCO is used to select which PHY will drive the UTP_RX_DATA
and UTP_RX_SOC signals. The PHY is selected by placing the PHY’s address on the
UTP_IP_ADDR and bringing UTP_OP_FCO to logic 1 during the current clock, followed by the
UTP_OP_FCO going to a logic 0 on the next clock cycle.
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-K
resistor.
Table 15.
UTOPIA Level 2/MII_A/ SMII[4] Interface (Sheet 9 of 9)
Name
Power
on
Reset
Normal
After
Reset
Until
Software
Enables
Normal
After
Software
Enables
Type
Description
NOTE:
This table discusses all features supported on the Intel IXP45X and Intel IXP46X Product Line of Network Processors. For details on feature support listed by processor,
see Table 1 on page 14.
For a legend of the Type codes, see Table 10 on page 46.
For information on selecting the desired interface, see the Intel
IXP45X and Intel IXP46X Product Line of Network Processors Developer’s Manual.
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