參數(shù)資料
型號(hào)： EWIXP460AC
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 400 MHz, RISC PROCESSOR, PBGA544
封裝： LEAD FREE, PLASTIC, BGA-544
文件頁數(shù)： 89/163頁
文件大小： 1123K
代理商： EWIXP460AC
Functional Overview
Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet
May 2005
Document Number: 306261-002
31
The SSP operates in master mode (the attached peripheral functions as a slave), and supports serial
bit rates from 7.2 Kbps to 1.8432 Mbps using the on-chip, 3.6864-MHz clock, and bit rates from
65.10 Kbps to 16.67 Mbps using a maximum off-chip, 33.33 MHz clock. Serial data formats may
range from 4 to 16 bits in length. Two on-chip register blocks function as independent FIFOs for
data, one for each direction. The FIFOs are 16 entries deep x 16 bits wide. Each 32-bit word from
the system fills one entry in a FIFO using the lower half 16-bits of a 32-bit word.
3.1.18
I2C Interface
The I
2C Bus Interface Unit allows the IXP45X/IXP46X network processors to serve as a master
and slave device residing on the I
2C bus. The I2C bus is a two-pin serial bus. SDA is the data pin
for input and output functions and SCL is the clock pin for reference and control of the I
2C bus.
The I
2C bus allows the IXP45X/IXP46X network processors to interface to other I2C peripherals
and micro-controllers for system management functions. The serial bus requires a minimum of
hardware for an economical system to relay status and reliability information on the IXP45X/
IXP46X network processors subsystem to an external device.
The I
2C Bus Interface Unit is a peripheral device that resides on the IXP45X/IXP46X network
processors’ APB. Data is transmitted to and received from the I
2C bus via a buffered interface.
Control and status information is relayed through a set of memory-mapped registers. Refer to the
I
2C Bus Specification for complete details on I2C bus operation.
The I
2C supports:
Multi-master capabilities
Slave capabilities
The I
2C unit supports both fast-mode operation — at 400 Kbps — and standard mode — at
100 Kbps. Fast mode logic levels, formats, capacitive loading and protocols function the same in
both modes. The I
2C unit does not support I2C 10-bit addressing or CBUS.
3.1.19
AES/DES/SHA/MD-5
The IXP45X/IXP46X network processors implement on-chip hardware acceleration for underlying
security and authentication algorithms.
The encryption/decryption algorithms supported are AES, single pass AES-CCM, DES, and triple
DES. These algorithms are commonly found when implementing IPSEC, VPN, WEP, WEP2,
WPA, and WPA2.
The authentication algorithms supported are MD-5, SHA-1, SHA-256, SHA-384, and SHA-512.
Inclusion of SHA-384 and SHA-512 allows 256-bit key authentication to pair up with 256-bit AES
support.
3.1.20
Cryptography Unit
The Cryptography Unit implements three major functions:
Exponentiation Unit (EAU)
Random Number Generator (RNG)
Secure Hash Algorithm (SHA function for the RNG)
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