參數(shù)資料
型號： EWIXP460AC
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 400 MHz, RISC PROCESSOR, PBGA544
封裝： LEAD FREE, PLASTIC, BGA-544
文件頁數(shù)： 80/163頁
文件大?。?/td> 1123K
代理商： EWIXP460AC
Functional Overview
Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet
May 2005
Document Number: 306261-002
23
The independent NPEs and MACs allow parallel processing of data traffic on the MII interfaces
and off loading of processing required by the Intel XScale core. The IXP45X/IXP46X network
processors are compliant with the IEEE 802.3 specification.
In addition to the MII interfaces, the IXP45X/IXP46X network processors include a single
management data interface that is used to configure and control PHY devices that are connected to
the MII interfaces. The IXP45X/IXP46X network processors provide support for serial media
independent interface (SMII).
3.1.4
UTOPIA Level 2
The integrated UTOPIA Level 2 interface works with a network-processing engine core for several
of the IXP45X/IXP46X network processors. The pins of the UTOPIA Level 2 interface are
multiplexed with one of the MII/SMII interfaces. (See Table 3 for details.)
The UTOPIA Level 2 interface supports a single- or a multiple-physical-interface configuration
with cell-level or octet-level handshaking. The network processing engine handles segmentation
and reassembly of ATM cells, CRC checking/generation, and transfer of data to/from memory.
This allows parallel processing of data traffic on the UTOPIA Level 2 interface, off-loading these
processing tasks from the Intel XScale core.
The IXP45X/IXP46X network processors are compliant with the ATM Forum, UTOPIA Level 2
Specification, Revision 1.0.
3.1.5
USB 1.1 Device Interface
The integrated USB 1.1 device interface supports full-speed operation and 16 endpoints and
includes an integrated transceiver.
There are:
Six isochronous endpoints (three input and three output)
One control endpoints
Three interrupt endpoints
Six bulk endpoints (three input and three output)
3.1.6
USB 2.0 Host Interface
USB Host functionality is implemented on the IXP45X/IXP46X network processors. The function
being performed is defined by the USB 2.0 specification, maintained by usb.org and the interface is
(largely) EHCI compliant, as defined by Intel.
Not all features defined by the 2.0 specification are supported for this implementation. The
following is a partial list of supported features:
Host function
Low-speed interface
Full-speed interface
EHCI register interface
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