參數(shù)資料
型號: EWIXP460AC
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: 400 MHz, RISC PROCESSOR, PBGA544
封裝: LEAD FREE, PLASTIC, BGA-544
文件頁數(shù): 88/163頁
文件大?。?/td> 1123K
代理商: EWIXP460AC
Functional Overview
May 2005
Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet
30
Document Number: 306261-002
The interrupt controller can configure each interrupt source as an FIQ, IRQ, or disabled. The
interrupt sources tied to Interrupt 0 to 7 can be prioritized. The remaining interrupts are prioritized
in ascending order. For example, Interrupt 8 has a higher priority than 9, 9 has a higher priority than
10, and 30 has a higher priority that 31.
An additional level of priority can be set for interrupts 32 through 64. This priority setting gives
any interrupt between 32 through 64 priority over interrupts 0 through 31.
3.1.15
Timers
The IXP45X/IXP46X network processors contain four internal timers operating at 66.667 MHz
(which is 2* OSC_IN input pin) to allow task scheduling and prevent software lock-ups. The
device has four 32-bit counters:
The Timestamp Timer and the two general-purpose timers have the optional ability to use a pre-
scaled clock. A programmable pre-scaler can be used to divide the input clock by a 16-bit value.
The input clock can be either the APB clock (66.66 MHz) or a 20-ns version of the APB clock
(50 MHz). By default all timers use the APB clock.
The 16-bit pre-scale value ranges from divide by 2 to 65,536 and results in a new clock enable
available for the timers that ranges from 33.33 MHz down to 1,017.26 Hz.
The Timestamp Timer also contains a 32-bit compare register that allows an interrupt to be created
at times other than time 0.
3.1.16
IEEE 1588 Hardware Assistance
In a distributed control system containing multiple clocks, individual clocks tend to drift apart.
Some kind of correction mechanism is necessary to synchronize the individual clocks to maintain
global time, which is accurate to some clock resolution. The IEEE 1588 standard for a precision
clock synchronization protocol for networked measurement and control systems can be used for
this purpose. The IEEE 1588 standard defines several messages that can be used to exchange
timing information.
The IXP45X/IXP46X network processors implement the IEEE 1588 hardware-assist logic on three
of the MII interfaces. Using the hardware assist logic along with software running on the Intel
XScale core, a full source or sink capable IEEE-1588 compliant network node can be
implemented.
Note:
The IXP455 network processor does not support IEEE 1588 hardware-assist.
3.1.17
Synchronous Serial Port Interface
The IXP45X/IXP46X network processors have a dedicated Synchronous Serial Port (SSP)
interface. The SSP interface is a full-duplex synchronous serial interface. It can connect to a variety
of external analog-to-digital (A/D) converters, audio and telecom CODECs, and many other
devices which use serial protocols for transferring data.
It supports National’s Microwire*, Texas Instruments’* synchronous serial protocol (SSP), and
Motorola's* serial peripheral interface (SPI*) protocol.
Watch-Dog Timer
Timestamp Timer
Two general-purpose Timers
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