參數(shù)資料
型號: EWIXP460AC
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: 400 MHz, RISC PROCESSOR, PBGA544
封裝: LEAD FREE, PLASTIC, BGA-544
文件頁數(shù): 54/163頁
文件大小: 1123K
代理商: EWIXP460AC
Electrical Specifications
Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet
May 2005
Document Number: 306261-002
147
Trdsetup
Data valid required before the rising edge of
EXP_MOT_DS_N
5.3
14.7
ns
Trdhold
Data hold required after the rising edge of
EXP_MOT_DS_N
2ns
Trecov
Time required between successive accesses on the
expansion interface.
116
Cycles
Figure 37.
HPI*–8 Mode Write Accesses
Table 69.
Motorola* Simplex Mode Values (Sheet 2 of 2)
Symbol
Parameter
Min.
Max.
Units
Notes
NOTES:
1. EX_ALE is not valid in simplex mode of operation.
2. Setting the address phase parameter (T1) will adjust the duration that the address appears to the external
device.
3. Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a data
strobe (read or write) to an external device.
4. Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears (read or
write) to an external device. Data will be available during this time as well.
5. Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects, address,
and data (during a write) will be held.
6. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
expansion interface.
7. T is the period of the clock measured in ns.
8. Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in
synchronous mode.
9. Timing was designed for a system load between 5pF and 60pF for high drive setting
EX_ADDR[2:1]
(hcntl)
EX_ADDR[0]
(hbil)
EX_RDY_N
(hrdy)
Data
EX_DATA
(hdin)
EX_CS_N
(hcs_n)
EX_WR_N
(hds1_n)
EX_RD_N
(hr_w_n)
Valid
Data
Valid
EX_CLK
T1
T3
T4
T3
T2
T4
T5
T1
T2
T5
Tadd_setup
Tcs2hds1val
Thds1_pulse
Tdata_setup
Tdata_hold
Trecov
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