- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄295917 > EWIXP460AC (INTEL CORP) 400 MHz, RISC PROCESSOR, PBGA544 PDF資料下載
參數(shù)資料
| 型號： | EWIXP460AC |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 400 MHz, RISC PROCESSOR, PBGA544 |
| 封裝： | LEAD FREE, PLASTIC, BGA-544 |
| 文件頁數(shù)： | 78/163頁 |
| 文件大?。?/td> | 1123K |
| 代理商： | EWIXP460AC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁當前第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁
Functional Overview
Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet
May 2005
Document Number: 306261-002
21
3.1.2
Internal Bus
The internal bus architecture of the IXP45X/IXP46X network processors are designed to allow
parallel processing to occur and to isolate bus utilization, based on particular traffic patterns. The
bus is segmented into four major buses:
3.1.2.1
North AHB
The North AHB is a 133.32-MHz (which is 4 * OSC_IN input pin), 32-bit bus that can be mastered
by the NPE A, NPE B, or NPE C. The targets of the North AHB can be the DDRI SDRAM or the
AHB/AHB bridge. The AHB/AHB bridge allows the NPEs to access the peripherals and internal
targets on the South AHB.
Data transfers by the NPEs on the North AHB to the South AHB are targeted predominately to the
queue manager. Transfers to the AHB/AHB bridge may be “posted” — when writing — or “split”
— when reading.
When a transaction is “posted,” a master on the North AHB requests a write to a peripheral on the
South AHB. If the AHB/AHB Bridge has a free FIFO location, the write request will be transferred
from the master on the North AHB to the AHB/AHB bridge. The AHB/AHB bridge will complete
the write on the South AHB, when it can obtain access to the peripheral on the South AHB. The
North AHB is released to complete another transaction.
When a transaction is “split,” a master on the North AHB requests a read of a peripheral on the
South AHB. If the AHB/AHB bridge has a free FIFO location, the read request will be transferred
from the master on the North AHB to the AHB/AHB bridge. The AHB/AHB bridge will complete
the read on the South AHB, when it can obtain access to the peripheral on the South AHB.
Once the AHB/AHB bridge has obtained the read information from the peripheral on the South
AHB, the AHB/AHB bridge notifies the arbiter, on the North AHB, that the AHB/AHB bridge has
the data for the master that requested the “split” transfer. The master on the North AHB — that
requested the split transfer — will arbitrate for the North AHB and transfer the read data from the
AHB/AHB bridge. The North AHB is released to complete another transaction while the North
AHB master — that requested the “split” transfer — waits for the data to arrive.
These “posting” and “splitting” transfers allow control of the North AHB to be given to another
master on the North AHB — enabling the North AHB to achieve maximum efficiency. Transfers to
the AHB/AHB bridge are considered to be small and infrequent, relative to the traffic passed
between the NPEs and the DDRI SDRAM on the North AHB.
When multiple masters arbitrate for the North AHB, the masters are awarded access to the bus in a
round-robin fashion. Each transaction can be no longer than an eight-word burst. This
implementation promotes fairness within the system.
3.1.2.2
South AHB
The South AHB is a 133.32-MHz (which is 4 * OSC_IN input pin), 32-bit bus that can be mastered
by the Intel XScale core, PCI controller, Expansion Bus Interface, USB Host Controller, and the
AHB/AHB bridge. The targets of the South AHB Bus can be the DDRI SDRAM, PCI Controller,
Queue Manager, Expansion Bus, or the AHB/APB bridge. As a special case, the Intel XScale
Core is the only master which can access the Cryptography Unit (target).
North Advanced, High-Performance Bus (AHB)
Memory Port Interface
South AHB
Advanced Peripheral Bus (APB)
相關PDF資料 |
PDF描述 |
|---|---|
| EWIXP455ABT | 266 MHz, RISC PROCESSOR, PBGA544 |
| EX5-R-PL | 16 CONTACT(S), MALE, COMBINATION LINE CONNECTOR, SOLDER |
| EXH2E106HR | PLASTIC FILM CAPACITORS |
| EXH2E205HR | PLASTIC FILM CAPACITORS |
| EXH2E255HR | PLASTIC FILM CAPACITORS |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EWIXP460BAD | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Intel 功能描述: |
| EWJKXA066A15 | 制造商:Panasonic Industrial Company 功能描述:CONTROL |
| EWK105BJ224MP-F | 制造商:TAIYO YUDEN 功能描述:Cut Tape 制造商:Taiyo Yuden 功能描述:Ceramic capacitor LWDC 0402 220nF 制造商:Taiyo Yuden 功能描述:Cap Ceramic 0.22uF 16V X5R 20% SMD 0204 85 制造商:Taiyo Yuden 功能描述:Cap Ceramic 0.22uF 16V X5R 20% SMD 0204 85°C Paper T/R |
| EWK105BJ224MPHF | 功能描述:CAP CER 0.22UF 16V X5R 0204 制造商:taiyo yuden 系列:LWDC?，LW 包裝:剪切帶（CT） 零件狀態(tài):在售 電容:0.22μF 容差:±20% 電壓 - 額定:16V 溫度系數(shù):X5R 工作溫度:-55°C ~ 85°C 特性:低 ESL 型（倒置結構） 等級:AEC-Q200 應用:汽車，旁通，去耦 故障率:- 安裝類型:表面貼裝，MLCC 封裝/外殼:0204（0610 公制） 大小/尺寸:0.020" 長 x 0.039" 寬（0.52mm x 1.00mm） 高度 - 安裝（最大值）:- 厚度（最大值）:0.014"（0.35mm） 引線間距:- 引線形式:- 標準包裝:1 |
| EWK105C6104MPHF | 功能描述:CAP CER 0.10UF 16V X6S 0204 制造商:taiyo yuden 系列:LWDC?，LW 包裝:剪切帶（CT） 零件狀態(tài):在售 電容:0.1μF 容差:±20% 電壓 - 額定:16V 溫度系數(shù):X6S 工作溫度:-55°C ~ 105°C 特性:低 ESL 型（倒置結構） 等級:AEC-Q200 應用:汽車，旁通，去耦 故障率:- 安裝類型:表面貼裝，MLCC 封裝/外殼:0204（0610 公制） 大小/尺寸:0.020" 長 x 0.039" 寬（0.52mm x 1.00mm） 高度 - 安裝（最大值）:- 厚度（最大值）:0.014"（0.35mm） 引線間距:- 引線形式:- 標準包裝:1 |
發(fā)布緊急采購，3分鐘左右您將得到回復。