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參數(shù)資料
| 型號(hào)： | EWIXP460AC |
| 廠商： | INTEL CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 400 MHz, RISC PROCESSOR, PBGA544 |
| 封裝： | LEAD FREE, PLASTIC, BGA-544 |
| 文件頁(yè)數(shù)： | 84/163頁(yè) |
| 文件大?。?/td> | 1123K |
| 代理商： | EWIXP460AC |
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Functional Overview
Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet
May 2005
Document Number: 306261-002
27
Legacy (16-bit, data mode)
Enhanced (32-bit, data mode)
3.1.9.1
Expansion Bus Legacy Mode of Operation
In the legacy mode of operation, the expansion interface is a 16-bit interface that allows an address
range of 512 bytes to 16 Mbytes, using 24 address lines for each of the eight independent chip
selects.
Accesses to the expansion bus interface is completed in five phases. Each of the five phases can be
lengthened or shortened by setting various configuration registers on a per-chip-select basis. This
feature allows the IXP45X/IXP46X network processors to connect to a wide variety of peripheral
devices with varying speeds.
The expansion interface supports Intel or Motorola* microprocessor-style bus cycles. The bus
cycles can be configured to be multiplexed address/data cycles or separate address/data cycles for
each of the eight chip-selects.
Additionally, Chip Selects 4 through 7 can be configured to support Texas Instruments* HPI-8 or
HPI-16 style accesses for DSPs.
The expansion interface is an asynchronous interface to externally connected chips. However, a
clock must be supplied to expansion interface of the IXP45X/IXP46X network processors for the
interface to operate. This clock can be driven from GPIO 15 or an external source. The maximum
clock rate that the expansion interface can accept in legacy mode of operation is 66 MHz. If GPIO
15 is used as the clock source, the Expansion Bus interface can only be clocked at a maximum of
33.32 MHz. GPIO 15’s maximum clock rate is 33.32 MHz.
By providing this legacy mode of operation, code developed for previous generations of this
platform becomes easily portable.
3.1.9.2
Expansion Bus Enhanced Mode of Operation
In the enhanced mode of operation, the expansion interface is a 32-bit interface that allows an
address range of 512 bytes to 32 Mbytes per chip select on IXP45X/IXP46X network processors,
using 25 address lines for each of the eight independent chip selects.
Additionally, in enhanced mode, the interface supports shared access to the bus with external
masters. This shared access is achieved with four request/grant pins and an integrated arbiter. Not
only can external devices access each other, but they can also access the IXP45X/IXP46X network
processors’ internal registers (including the DDRI SDRAM interface).
The advantage to this feature is that shared memory access can be achieved by using the DDRI
SDRAM interface attached to IXP45X/IXP46X network processors. This lowers the system’s
overall bill of materials.
Enhanced mode also supports synchronous transfers at speeds of up to 80 MHz with a 40-pF load.
In addition to fully synchronous support, the enhanced mode also supports burst transfers of up to
eight-word lengths. The synchronous bus support is compatible to Zero Bus Turnaround (ZBT)
SRAM cycles for inbound/outbound transactions for both read/write transactions.
Additionally, the outbound read transactions can support the Intel StrataFlash
K3 synchronous-
burst support.
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