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參數(shù)資料
| 型號： | GE28F128W30T90 |
| 英文描述： | EEPROM|FLASH|8MX16|CMOS|BGA|60PIN|PLASTIC |
| 中文描述： | 的EEPROM | FLASH動畫| 8M × 16位|的CMOS | BGA封裝| 60PIN |塑料 |
| 文件頁數(shù)： | 48/91頁 |
| 文件大?。?/td> | 994K |
| 代理商： | GE28F128W30T90 |
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1.8 Volt Intel
Wireless Flash Memory with 3 Volt I/O
48
Datasheet
When the device is operating in asynchronous page mode or asynchronous single word read mode,
WAIT is set to an “asserted” state as determined by CR[10]. See
Figure 21, “Page-Mode Read
Operation Waveform” on page 63
, and
Figure 19, “Asynchronous Read Operation Waveform” on
page 61
.
From a system perspective, the WAIT signal is in the asserted state (based on CR[10]) when the
device is operating in synchronous non-read-array mode (such as Read ID, Read Query, or Read
Status), or if the device is operating in asynchronous mode (CR[15]=1). In these cases, the system
software should ignore (mask) the WAIT signal, because it does not convey any useful information
about the validity of what is appearing on the data bus.
8.5
Data Hold (CR[9])
The Data Output Configuration bit (CR[9]) determines whether a data word remains valid on the
data bus for one or two clock cycles. The processor’s minimum data set-up time and the flash
memory’s clock-to-data output delay determine whether one or two clocks are needed.
A Data Output Configuration set at 1-clock data hold corresponds to a 1-clock data cycle; a Data
Output Configuration set at 2-clock data hold corresponds to a 2-clock data cycle. The setting of
this configuration bit depends on the system and CPU characteristics. For clarification, see
Figure
18, “Data Output Configuration with WAIT Signal Delay” on page 49
.
A method for determining this configuration setting is shown below.
To set the device at 1-clock data hold for subsequent reads, the following condition must be
satisfied:
t
CHQV (ns) +
t
DATA
(ns)
≤
One CLK Period (ns)
As an example, use a clock frequency of 54 MHz and a clock period of 25 ns. Assume the data
output hold time is one clock. Apply this data to the formula above for the subsequent reads:
20 ns + 4 ns
≤
25 ns
This equation is satisfied, and data output will be available and valid at every clock period. If t
DATA
is long, hold for two cycles.
During page-mode reads, the initial access time can be determined by the formula:
t
ADD-DELAY (ns) +
t
DATA
(ns)
+
t
AVQV
(ns)
CONDITION
WAIT
CE# = V
IH
CE# = V
IL
OE#
Tri-State
Active
No-Effect
Synchronous Array Read
Active
Synchronous Non-Array Read
Asserted
All Asynchronous Read and all Write
Asserted
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