參數(shù)資料
型號(hào)： GE28F128W30T90
英文描述： EEPROM|FLASH|8MX16|CMOS|BGA|60PIN|PLASTIC
中文描述： 的EEPROM | FLASH動(dòng)畫(huà)| 8M × 16位|的CMOS | BGA封裝| 60PIN |塑料
文件頁(yè)數(shù)： 49/91頁(yè)
文件大?。?/td> 994K
代理商： GE28F128W30T90
1.8 Volt Intel
Wireless Flash Memory with 3 Volt I/O
Datasheet
49
Subsequent reads in page mode are defined by:
t
APA (ns) +
t
DATA
(ns)
(minimum time)
NOTE:
WAIT shown asserted high (CR[10]=1).
8.6
WAIT Delay (CR[8])
The WAIT configuration bit (CR[8]) controls WAIT signal delay behavior for all synchronous
read-array modes. Its setting depends on the system and CPU characteristics. The WAIT can be
asserted either during, or one data
cycle
before, a valid output.
In synchronous linear read array (no-wrap mode CR[3]=1) of 4-, 8-, 16-, or continuous-word burst
mode, an output delay may occur when a burst sequence crosses its first device-row boundary (16-
word boundary). If the burst start address is 4-word boundary aligned, the delay does not occur. If
the start address is misaligned to a 4-word boundary, the delay occurs once per burst-mode read
sequence. The WAIT signal informs the system of this delay.
8.7
Burst Sequence (CR[7])
The burst sequence specifies the synchronous-burst mode data order (see
Table 16, “Sequence and
Burst Length” on page 50
). Set this bit for linear or Intel burst order. Continuous burst mode
supports only linear burst order.
When operating in a linear burst mode, either 4-, 8-, or 16-word burst length with the burst wrap bit
(CR[3]) set, or in continuous burst mode, the device may incur an output delay when the burst
sequence crosses the first 16-word boundary. (See
Figure 16, “Word Boundary” on page 46
for
word boundary description.) This depends on the starting address. If the starting address is aligned
to a 4-word boundary, there is no delay. If the starting address is the end of a 4-word boundary, the
output delay is one clock cycle less than the First Access Latency Count; this is the worst-case
Figure 18. Data Output Configuration with WAIT Signal Delay
DQ
15-0
[Q]
CLK [C]
Valid
Output
Valid
Output
Valid
Output
DQ
15-0
[Q]
Valid
Output
1 CLK
Data Hold
WAIT (CR.8 = 1)
WAIT (CR.8 = 0)
t
CHQV
t
CHQV
WAIT (CR.8 = 0)
WAIT (CR.8 =1)
2 CLK
Data Hold
t
CHTL/H
Note 1
Note 1
Note 1
Note 1
Valid
Output
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