參數(shù)資料
型號(hào)： GE28F640W30T70
英文描述： EEPROM|FLASH|4MX16|CMOS|BGA|56PIN|PLASTIC
中文描述： 的EEPROM | FLASH動(dòng)畫(huà)| 4MX16 |的CMOS | BGA封裝| 56PIN |塑料
文件頁(yè)數(shù)： 16/91頁(yè)
文件大?。?/td> 994K
代理商： GE28F640W30T70
1.8 Volt Intel
Wireless Flash Memory with 3 Volt I/O
16
Datasheet
ADV#). In synchronous mode, the address is latched by either the rising edge of ADV# or the
rising (or falling) CLK edge while ADV# remains asserted, whichever occurs first. WE# and RST#
must be at deasserted during read operations.
3.1.2
Burst Suspend
The Burst Suspend feature allows the system to temporarily suspend a synchronous burst operation
if the system needs to use the flash address and data bus for other purposes. Burst accesses can be
suspended during the initial latency (before data is received) or after the device has output data.
When a burst access is suspended, internal array sensing continues and any previously latched
internal data is retained.
Burst Suspend occurs when CE# is asserted, the current address has been latched (either ADV#
rising edge or valid CLK edge), CLK is halted, and OE# is deasserted. CLK can be halted when it
is at V
IH
or V
IL
. To resume the burst access, OE# is reasserted and CLK is restarted. Subsequent
CLK edges resume the burst sequence where it left off.
Within the device, CE# gates WAIT. Therefore, during Burst Suspend WAIT remains asserted and
does not revert to a high-impedance state when OE# is deasserted. This can cause contention with
another device attempting to control the system’s READY signal during a Burst Suspend. System
using the Burst Suspend feature should not connect the device’s WAIT signal directly to the
system’s READY signal.
Refer to
Figure 26, “Burst Suspend” on page 68
.
3.1.3
Standby
De-asserting CE# deselects the device and places it in standby mode, substantially reducing device
power consumption. In standby mode, outputs are placed in a high-impedance state independent of
OE#. If deselected during a program or erase algorithm, the device shall consume active power
until the program or erase operation completes.
3.1.4
Reset
The device enters a reset mode when RST# is asserted. In reset mode, internal circuitry is turned
off and outputs are placed in a high-impedance state.
After returning from reset, a time t
PHQV
is required until outputs are valid, and a delay (t
PHWV
) is
required before a write sequence can be initiated. After this wake-up interval, normal operation is
restored. The device defaults to read-array mode, the status register is set to 80h, and the
configuration register defaults to asynchronous page-mode reads.
If RST# is asserted during an erase or program operation, the operation aborts and the memory
contents at the aborted block or address are invalid. See
Figure 32, “Reset Operations Waveforms”
on page 74
for detailed information regarding reset timings.
Like any automated device, it is important to assert RST# during system reset. When the system
comes out of reset, the processor expects to read from the flash memory array. Automated flash
memories provide status information when read during program or erase operations. If a CPU reset
occurs with no flash memory reset, proper CPU initialization may not occur because the flash
memory may be providing status information instead of array data. 1.8 Volt Intel Flash memories
allow proper CPU initialization following a system reset through the use of the RST# input. In this
application, RST# is controlled by the same CPU reset signal, RESET#.
相關(guān)PDF資料
PDF描述
GE28F640W30T85 EEPROM|FLASH|4MX16|CMOS|BGA|56PIN|PLASTIC
GF4435 TRANSISTOR | MOSFET | P-CHANNEL | 30V V(BR)DSS | 8A I(D) | SO
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GE28F640W30T85 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM|FLASH|4MX16|CMOS|BGA|56PIN|PLASTIC
GE28F800B3BA90 制造商:Intel 功能描述:NOR Flash, 512K x 16, 45 Pin, Plastic, BGA
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GE28F800C3BA70 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced+ Boot Block Flash Memory (C3)
GE28F800C3BA90 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced+ Boot Block Flash Memory (C3)
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