參數(shù)資料
型號(hào): GE28F640W30T70
英文描述: EEPROM|FLASH|4MX16|CMOS|BGA|56PIN|PLASTIC
中文描述: 的EEPROM | FLASH動(dòng)畫| 4MX16 |的CMOS | BGA封裝| 56PIN |塑料
文件頁(yè)數(shù): 9/91頁(yè)
文件大小: 994K
代理商: GE28F640W30T70
1.8 Volt Intel
Wireless Flash Memory with 3 Volt I/O
Datasheet
9
The memory architecture for the 1.8 Volt Intel Wireless Flash memory consists of multiple 4-Mbit
partitions, the exact number depending on device density. By dividing the memory array into
partitions, program or erase operations can take place simultaneously during read operations. Burst
reads can traverse partition boundaries, but user application code is responsible for ensuring that
they don’t extend into a partition that is actively programming or erasing. Although each partition
has burst-read, write, and erase capabilities, simultaneous operation is limited to write or erase in
one partition while other partitions are in a read mode.
Augmented erase-suspend functionality further enhances the RWW capabilities of this device. An
erase can be suspended to perform a program or read operation within any block, except that which
is erase-suspended. A program operation nested within a suspended erase can subsequently be
suspended to read yet another memory location.
After device power-up or reset, the 1.8 Volt Intel Wireless Flash memory defaults to asynchronous
read configuration. Writing to the device’s configuration register enables synchronous burst-mode
read operation. In synchronous mode, the CLK input increments an internal burst address
generator. CLK also synchronizes the flash memory with the host CPU and outputs data on every,
or on every other, valid CLK cycle after an initial latency. A programmable WAIT output signals to
the CPU when data from the flash memory device is ready.
In addition to its improved architecture and interface, the 1.8 Volt Intel Wireless Flash memory
with 3 Volt I/O incorporates Enhanced Factory Programming (EFP), a feature that enables fast
programming and low-power designs. The EFP feature provides the fastest currently-available
program performance, which can increase a factory’s manufacturing throughput.
The device supports read operations at 1.8 V and erase and program operations at 1.8 V or 12 V.
With the 1.8-V option, VCC and VPP can be tied together for a simple, ultra-low-power design. In
addition to voltage flexibility, the dedicated VPP input provides complete data protection when
V
PP
V
PPLK
.
A 128-bit protection register enhances the user’s ability to implement new security techniques and
data protection schemes. Unique flash device identification and fraud-, cloning-, or content-
protection schemes are possible through a combination of factory-programmed and user-OTP data
cells. Zero-latency locking/unlocking on any memory block provides instant and complete
protection for critical system code and data. An additional block lock-down capability provides
hardware protection where software commands alone cannot change the block’s protection status.
The device’s Command User Interface (CUI) is the system processor’s link to internal flash
memory operation. A valid command sequence written to the CUI initiates device Write State
Machine (WSM) operation that automatically executes the algorithms, timings, and verifications
necessary to manage flash memory program and erase. An internal status register provides ready/
busy indication results of the operation (success, fail, and so on).
Three power-saving features– Automatic Power Savings (APS), standby, and RST#– can
significantly reduce power consumption. The device automatically enters APS mode following
read cycle completion. Standby mode begins when the system deselects the flash memory by
de-asserting CE#. Driving RST# low produces power savings similar to standby mode. It also
resets the part to read-array mode (important for system-level reset), clears internal status registers,
and provides an additional level of flash write protection.
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相關(guān)代理商/技術(shù)參數(shù)
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