參數(shù)資料
型號(hào): GE28F640W30T70
英文描述: EEPROM|FLASH|4MX16|CMOS|BGA|56PIN|PLASTIC
中文描述: 的EEPROM | FLASH動(dòng)畫| 4MX16 |的CMOS | BGA封裝| 56PIN |塑料
文件頁數(shù): 46/91頁
文件大?。?/td> 994K
代理商: GE28F640W30T70
1.8 Volt Intel
Wireless Flash Memory with 3 Volt I/O
46
Datasheet
)
NOTE:
The 16-word boundary is the end of the device sense word-line.
Parameters defined by CPU
:
t
ADD-DELAY
= Clock to CE#, ADV#, or Address Valid, whichever occurs last.
t
DATA
= Data setup to Clock.
Parameters defined by flash
:
t
AVQV
= Address to Output Delay.
Example:
CPU Clock Speed = 40 MHz
t
ADD-DELAY
= 6 ns (typical speed from CPU) (max)
t
DATA
= 4 ns (typical speed from CPU) (min)
t
AVQV
= 70 ns (from AC Characteristic - Read Only Operations Table)
From Eq. (1):
1/40 (MHz) = 25 ns
From Eq. (2)
n(25 ns)
70 ns + 6 ns + 4 ns
n(25 ns)
80 ns
n
80/25 = 3.2
=
4
(Integer)
From Eq. (3)
n - 1= 4 - 1 = 3 (assuming the starting address is at the 4-
word unaligned, must use n-1)
Table 15. First Latency Count (LC)
LC Setting
Burst
Length
Wrap
Aligned to 4-word
Boundary
WAIT Asserted on 16-Word
Boundary Crossing
n–1
4, 8, 16
Disabled
No
Yes, Occurs on Every 16 word
boundary crossing
n–2
4, 8, 16
Disabled
Yes
No
n–2
4, 8, 16
Enabled
No
No
n–2
4, 8, 16
Enabled
Yes
No
n–1
Continuous
X
X
Yes, Occurs Once
1
NOTE:
1. See
Section 8.10, “Burst Length (CR[2:0])” on page 52
for details.
Figure 16. Word Boundary
0
1
2
3
4
5
6
7
8
9
A
B C D E
F
16 Word Boundary
Word 0 - 3
Word 4 - 7
Word 8 - B
Word C - F
4 Word Boundary
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